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Rajiv V. Joshi: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hamed F. Dadgour, Rajiv V. Joshi, Kaustav Banerjee
    A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:977-982 [Conf]
  2. Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif
    Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:69-72 [Conf]
  3. Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
    SOI for asynchronous dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:37-42 [Conf]
  4. Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri
    Design and CAD Challenges in sub-90nm CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:129-137 [Conf]
  5. Wei Hwang, Rajiv V. Joshi, Walter H. Henkels
    A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:712-717 [Conf]
  6. Jente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi
    A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:574-584 [Conf]
  7. W. K. Luk, Y. Katayama, Wei Hwang, M. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
    Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:279-285 [Conf]
  8. W. Chen, Wei Hwang, P. Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
    Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:263-266 [Conf]
  9. Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang, Peter W. Cook, Richard B. Brown
    New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:168-171 [Conf]
  10. Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
    "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:203-206 [Conf]
  11. Keunwoo Kim, Koushik K. Das, Rajiv V. Joshi, Ching-Te Chuang
    Nanoscale CMOS circuit leakage power reduction by double-gate device. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:102-107 [Conf]
  12. Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang
    Strained-si devices and circuits for low-power applications. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:180-183 [Conf]
  13. Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim
    Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:153-158 [Conf]
  14. Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi
    Design of sub-90nm Circuits and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:3-4 [Conf]
  15. Rajiv V. Joshi, Kaustav Banerjee, André DeHon
    Tutorial 1: Emerging Technologies for VLSI Design. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:4- [Conf]
  16. Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy
    Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:410-415 [Conf]
  17. Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif
    Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:33-40 [Conf]
  18. Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty
    IBM's Blue Logic Design Methodology-Circuits and Physical Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:11-12 [Conf]
  19. Rajiv V. Joshi, Wei Hwang
    Design Considerations and Implementation of a High Performance Dynamic Register File. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:526-531 [Conf]
  20. Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
    Design Of Provably Correct Storage Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:196-0 [Conf]
  21. Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang
    A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:44-49 [Conf]
  22. Rajiv V. Joshi, K. Kroell, Ching-Te Chuang
    A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2004, pp:832-0 [Conf]
  23. Rajiv V. Joshi, S. S. Kang, N. Zamdmar, A. Mocuta, Ching-Te Chuang, J. A. Pascual-Gutiérrez
    Direct Temperature Measurement for VLSI Circuits and 3-D Modeling of Self-Heating in Sub-0.13 mum SOI Technologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2005, pp:697-702 [Conf]
  24. Rajiv V. Joshi, Kaushik Roy
    Design of Deep Sub-Micron CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:15-16 [Conf]
  25. Ruchir Puri, Tanay Karnik, Rajiv V. Joshi
    Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:5-7 [Conf]
  26. Rajiv V. Joshi, Keunwoo Kim, Richard Q. Williams, Edward J. Nowak, Ching-Te Chuang
    A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:665-672 [Conf]
  27. Stephen V. Kosonocky, Arthur A. Bright, Kevin Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin Stawiasz
    Designing a Testable System on a Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:2-7 [Conf]
  28. E. N. Elnozahy, Rajiv V. Joshi
    Preface. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:521-524 [Journal]
  29. Rajiv V. Joshi, Ching-Te Chuang, S. K. H. Fung, Fari Assaderaghi, Melanie Sherony, I. Yang, Ghavam V. Shahidi
    PD/SOI SRAM performance in presence of gate-to-body tunneling current. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1106-1113 [Journal]

  30. An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects. [Citation Graph (, )][DBLP]


  31. A floating-body dynamic supply boosting technique for low-voltage sram in nanoscale PD/SOI CMOS technologies. [Citation Graph (, )][DBLP]


  32. SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. [Citation Graph (, )][DBLP]


  33. Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives. [Citation Graph (, )][DBLP]


  34. Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield. [Citation Graph (, )][DBLP]


  35. A Root-Finding Method for Assessing SRAM Stability. [Citation Graph (, )][DBLP]


  36. Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. [Citation Graph (, )][DBLP]


  37. Statistical yield analysis of silicon-on-insulator embedded DRAM. [Citation Graph (, )][DBLP]


  38. The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]


  39. Use of scalable Parametric Measurement Macro to improve semiconductor technology characterization and product test. [Citation Graph (, )][DBLP]


  40. FinFET SRAM Design. [Citation Graph (, )][DBLP]


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