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Walter Daems:
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- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. [Citation Graph (0, 0)][DBLP] DAC, 2002, pp:431-436 [Conf]
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP] DAC, 1999, pp:958-963 [Conf]
- Geert Van der Plas, Jan Vandenbussche, Walter Daems, Antal van den Bosch, Georges G. E. Gielen, Willy M. C. Sansen
Systematic design of a 14-bit 150-MS/s CMOS current-steering D/A converter. [Citation Graph (0, 0)][DBLP] DAC, 2000, pp:452-457 [Conf]
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
A Fitting Approach to Generate Symbolic Expressions for Linear and Nonlinear Analog Circuit Performance Characteristics. [Citation Graph (0, 0)][DBLP] DATE, 2002, pp:268-273 [Conf]
- Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
Generalized Posynomial Performance Modeling. [Citation Graph (0, 0)][DBLP] DATE, 2003, pp:10250-10255 [Conf]
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing. [Citation Graph (0, 0)][DBLP] ICCAD, 2001, pp:70-74 [Conf]
- Francky Leyn, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
A behavioral signal path modeling methodology for qualitative insight in and efficient sizing of CMOS opamps. [Citation Graph (0, 0)][DBLP] ICCAD, 1997, pp:374-381 [Conf]
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
Circuit simplification for the symbolic analysis of analogintegrated circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:395-407 [Journal]
- Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits. [Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:5, pp:517-534 [Journal]
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