The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Qiuyang Wu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ajay J. Daga, Loa Mize, Subramanyam Sripada, Chris Wolff, Qiuyang Wu
    Automated timing model generation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:146-151 [Conf]
  2. K. A. Rajagopal, R. Sivakumar, N. V. Arvind, C. Sreeram, Vish Visvanathan, Shailendra Dhuri, Roopesh Chander, Patrick Fortner, Subra Sripada, Qiuyang Wu
    A Comprehensive Solution for True Hierarchical Timing and Crosstalk Delay Signoff. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:277-282 [Conf]

Search in 0.001secs, Finished in 0.001secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002