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Shishpal Rawat: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta
    COT - customer owned trouble. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:91-92 [Conf]
  2. David L. Dill, Nate James, Shishpal Rawat, Gérard Berry, Limor Fix, Harry Foster, Rajeev K. Ranjan, Gunnar Stålmarck, Curt Widdoes
    Formal verification methods: getting around the brick wall. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:576-577 [Conf]
  3. Rajesh K. Gupta, Shishpal Rawat, Sandeep K. Shukla, Brian Bailey, Daniel K. Beece, Masahiro Fujita, Carl Pixley, John O'Leary, Fabio Somenzi
    Formal verification - prove it or pitch it. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:710-711 [Conf]
  4. Rajesh K. Gupta, Shishpal Rawat, Ingrid Verbauwhede, Gérard Berry, Ramesh Chandra, Daniel Gajski, Kris Konigsfeld, Patrick Schaumont
    Panel: The Next HDL: If C++ is the Answer, What was the Question? [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:71-72 [Conf]
  5. Shishpal Rawat, Raul Camposano, A. Kahng, Joseph Sawicki, Mike Gianfagna, Naeem Zafar, A. Sharan
    DFM: where's the proof of value? [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1061-1062 [Conf]
  6. Shishpal Rawat, William H. Joyner Jr., John A. Darringer, Daniel Gajski, Pat O. Pistilli, Hugo De Man, Carl Harris, James Solomon
    Were the good old days all that good?: EDA then and now. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:543- [Conf]
  7. Paul G. Ryan, Shishpal Rawat, W. Kent Fuchs
    Two-Stage Fault Location. [Citation Graph (0, 0)][DBLP]
    ITC, 1991, pp:963-968 [Conf]
  8. Tin-Fook Ngai, Mary Jane Irwin, Shishpal Rawat
    Regular Area-Time Efficient Carry-Lookahead Adders. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1986, v:3, n:1, pp:92-105 [Journal]
  9. T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson
    EDA challenges facing future microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1498-1506 [Journal]
  10. Shishpal Rawat, Hans-Joachim Wunderlich
    Introduction. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2003, v:8, n:4, pp:397-398 [Journal]

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