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Naveed A. Sherwani: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Robert Dahlberg, Shishpal Rawat, Jen Bernier, Gina Gloski, Aurangzeb Khan, Kaushik Patel, Paul Ruddy, Naveed A. Sherwani, Ronnie Vasishta
    COT - customer owned trouble. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:91-92 [Conf]
  2. Roshan A. Gidwani, Naveed A. Sherwani
    MISER: An Integrated Three Layer Gridless Channel Router and Compactor. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:698-703 [Conf]
  3. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    New Algorithm for Over-the-Cell Channel Routing Using Vacant Terminals. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:126-131 [Conf]
  4. Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
    A Unified Approach to Multilayer Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:182-187 [Conf]
  5. Sivakumar Natarajan, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh
    Over-the-Cell Channel Routing for High Performance Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:600-603 [Conf]
  6. Naveed A. Sherwani, Jitender S. Deogun
    A New Heuristic for Single Row Routing Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:167-172 [Conf]
  7. Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan
    DFM rules! [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:168-169 [Conf]
  8. Bo Wu, Naveed A. Sherwani, Nancy D. Holmes, Majid Sarrafzadeh
    Over-the-Cell Routers for New Cell Model. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:604-607 [Conf]
  9. Qiong Yu, Sandeep Badida, Naveed A. Sherwani
    Algorithmic Aspects of Three Dimensional MCM Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:397-401 [Conf]
  10. Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani, A. Sureka
    OPRON: a new approach to planar OTC routing. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:208-212 [Conf]
  11. Dinesh P. Mehta, Naveed A. Sherwani
    A Minimum-Area Floorplanning Algorithm for MBC Designs. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:56-59 [Conf]
  12. Surendra Burman, Chandar Kamalanathan, Naveed A. Sherwani
    New channel segmentation model and associated routing algorithm for high performance FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:22-25 [Conf]
  13. Hung-Ming Chen, Hai Zhou, Fung Yu Young, D. F. Wong, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning and interconnect planning. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:354-357 [Conf]
  14. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    Algorithms for Three-Layer Over-The-Cell Channel Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:428-431 [Conf]
  15. Moazzem Hossain, Naveed A. Sherwani
    On Topological Via Minimization and Routing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:532-535 [Conf]
  16. Wasim Khan, Moazzem Hossain, Naveed A. Sherwani
    Zero skew clock routing in multiple-clock synchronous systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:464-467 [Conf]
  17. S. Miriyala, Jahangir A. Hashmi, Naveed A. Sherwani
    Switchbox Steiner Tree Problem in Presence of Obstacles. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:536-539 [Conf]
  18. Alfred J. Boals, Ajay K. Gupta, Jahangir A. Hashmi, Naveed A. Sherwani
    Compact Hypercubes: Properties and Recognition. [Citation Graph (0, 0)][DBLP]
    ICCI, 1991, pp:395-402 [Conf]
  19. Alfred J. Boals, Ajay K. Gupta, Jahangir A. Hashmi, Naveed A. Sherwani
    An Efficient Approximation Algorithm for Hypercube Scheduling. [Citation Graph (0, 0)][DBLP]
    ICCI, 1991, pp:474-483 [Conf]
  20. Ajay K. Gupta, Alfred J. Boals, Naveed A. Sherwani
    On Optimal Embeddings into Incomplete Hypercubes. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:416-423 [Conf]
  21. Venkata K. Prabhala, Naveed A. Sherwani
    Fully Normal Algorithms for Incomplete Hypercubes. [Citation Graph (0, 0)][DBLP]
    IPPS, 1991, pp:144-150 [Conf]
  22. Pramod Anne, Aditya Reddy, Naveed A. Sherwani, Anand Panyam, Siddharth Bhingarde
    Comparative Analysis of New CMOS Leaf Cells for OTC Routing. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:191-194 [Conf]
  23. Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
    Efficient Over-the-cell Routing Algorithm for General Middle Terminal Model. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1861-1864 [Conf]
  24. Wasim Khan, Sreekrishna Madhwapathy, Naveed A. Sherwani
    A Hierarchical Approach to Clock Routing in High Performance Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:467-470 [Conf]
  25. Sreekrishna Madhwapathy, Naveed A. Sherwani, Siddharth Bhingarde, Anand Panyam
    An Efficient Four Layer Over-the-Cell Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:187-190 [Conf]
  26. Naveed A. Sherwani
    The bottom-10 problems in EDA (panel session (title only)). [Citation Graph (0, 0)][DBLP]
    ISPD, 2000, pp:39- [Conf]
  27. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Naveed A. Sherwani
    Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2002, pp:56-61 [Conf]
  28. Jeff Parkhurst, Naveed A. Sherwani, Sury Maturi, Dana Ahrams, Eli Chiprout
    SRC physical design top ten problem. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:55-58 [Conf]
  29. Siddharth Bhingarde, Rafay Khawaja, Anand Panyam, Naveed A. Sherwani
    Over-the-Cell Routing Algorithms for Industrial Cell Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:143-148 [Conf]
  30. Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
    On Optimum Cell Models for Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:94-99 [Conf]
  31. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
    A Provably Good Algorithm for k-Layer Topological Planar Routing Problems. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1993, pp:113- [Conf]
  32. Jim E. Crenshaw, Spyros Tragoudas, Naveed A. Sherwani
    High Performance Over-the-Cell Routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:137-142 [Conf]
  33. Srinivasa R. Danda, Sreekrishna Madhwapathy, Naveed A. Sherwani
    Optimal algorithms for planar over-the-cell routing in the presence of obstacles. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:3-7 [Conf]
  34. Dinesh P. Mehta, Naveed A. Sherwani, A. Bariya
    T3: Physical Design. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:3-0 [Conf]
  35. Naveed A. Sherwani, Prashant Sawkar
    Embedded Tutorial: Layout Driven Synthesis or Synthesis Driven Layout. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1998, pp:44-47 [Conf]
  36. Dana L. Grinstead, Peter J. Slater, Naveed A. Sherwani, Nancy D. Holmes
    Efficient Edge Domination Problems in Graphs. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 1993, v:48, n:5, pp:221-228 [Journal]
  37. Jason Cong, Moazzem Hossain, Naveed A. Sherwani
    A provably good multilayer topological planar routing algorithm in IC layout designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:1, pp:70-78 [Journal]
  38. Srinivasa R. Danda, Xiaolin Liu, Sreekrishna Madhwapathy, Anand Panyam, Naveed A. Sherwani, Ioannis G. Tollis
    Optimal algorithms for planar over-the-cell routing problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:11, pp:1365-1378 [Journal]
  39. Nancy D. Holmes, Naveed A. Sherwani, Majid Sarrafzadeh
    Utilization of vacant terminals for improved over-the-cell channel routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:6, pp:780-792 [Journal]
  40. T. Karn, Shishpal Rawat, Desmond Kirkpatrick, Rabindra Roy, Greg Spirakis, Naveed A. Sherwani, Craig Peterson
    EDA challenges facing future microprocessor design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:12, pp:1498-1506 [Journal]
  41. Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani
    Integrated floorplanning with buffer/channel insertion for bus-based designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:730-741 [Journal]
  42. Dinesh P. Mehta, Naveed A. Sherwani
    On the use of flexible, rectilinear blocks to obtain minimum-area floorplans in mixed block and cell designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:1, pp:82-97 [Journal]
  43. Siddharth Bhingarde, Anand Panyam, Naveed A. Sherwani
    Middle terminal cell models for efficient over-the-cell routing in high-performance circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:4, pp:462-472 [Journal]

  44. Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs. [Citation Graph (, )][DBLP]


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