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Peter Lidén:
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Publications of Author
- Peter Dahlgren, Peter Lidén
Modeling of Intermediate Node States in switch-Level Networks. [Citation Graph (0, 0)][DBLP] DAC, 1994, pp:722-727 [Conf]
- Peter Dahlgren, Peter Lidén
A Switch-level Algorithm for Simulation of Transients in Combinational Logic. [Citation Graph (0, 0)][DBLP] FTCS, 1995, pp:207-216 [Conf]
- Peter Lidén, Peter Dahlgren, Rolf Johansson, Johan Karlsson
On Latching Probability of Particle Induced Transients in Combinational Networks. [Citation Graph (0, 0)][DBLP] FTCS, 1994, pp:340-349 [Conf]
- Peter Dahlgren, Peter Lidén
Efficient modeling of switch-level networks containing undetermined logic node states. [Citation Graph (0, 0)][DBLP] ICCAD, 1993, pp:746-752 [Conf]
- Peter Lidén, Peter Dahlgren
Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. [Citation Graph (0, 0)][DBLP] ISCAS, 1995, pp:2124-2127 [Conf]
- Johan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin
Two Fault Injection Techniques for Test of Fault Handling Mechanisms. [Citation Graph (0, 0)][DBLP] ITC, 1991, pp:140-149 [Conf]
- Peter Lidén, Peter Dahlgren, Jan Torin
Transistor Fault Coverage for Self-Testing CMOS Checkers. [Citation Graph (0, 0)][DBLP] ITC, 1992, pp:476-485 [Conf]
- Peter Dahlgren, Peter Lidén
A fault model for switch-level simulation of gate-to-drain shorts. [Citation Graph (0, 0)][DBLP] VTS, 1996, pp:414-421 [Conf]
- Peter Lidén, Peter Dahlgren
Switch-level modeling of transistor-level stuck-at faults. [Citation Graph (0, 0)][DBLP] VTS, 1995, pp:208-215 [Conf]
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