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Shantanu Dutt: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shantanu Dutt, Wenyong Deng
    A Probability-Based Approach to VLSI Circuit Partitioning. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:100-105 [Conf]
  2. Vinay Verma, Shantanu Dutt, Vishal Suthar
    Efficient on-line testing of FPGAs with provable diagnosabilities. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:498-503 [Conf]
  3. Ke Zhong, Shantanu Dutt
    Algorithms for simultaneous satisfaction of multiple constraints and objective optimization in a placement flow with application to congestion control. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:854-859 [Conf]
  4. Shantanu Dutt, Hasan Arslan
    Efficient timing-driven incremental routing for VLSI circuits using DFS and localized slack-satisfaction computations. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:768-773 [Conf]
  5. Vishal Suthar, Shantanu Dutt
    Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults. [Citation Graph (0, 0)][DBLP]
    DATE, 2006, pp:1165-1170 [Conf]
  6. Federico Rota, Shantanu Dutt, Sahithi Krishna
    Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:507-515 [Conf]
  7. Vinay Verma, Shantanu Dutt
    Roving testing using new built-in-self-tester designs for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2004, pp:257- [Conf]
  8. Fikri T. Assaad, Shantanu Dutt
    More Robust Tests in Algorithm-Based Fault-Tolerant Matrix Multiplication. [Citation Graph (0, 0)][DBLP]
    FTCS, 1992, pp:430-439 [Conf]
  9. Shantanu Dutt, John P. Hayes
    Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP]
    FTCS, 1991, pp:292-299 [Conf]
  10. Shantanu Dutt, Nihar R. Mahapatra
    Node Covering, Error Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:320-329 [Conf]
  11. Nihar R. Mahapatra, Shantanu Dutt
    Hardware-Efficient and Highly-Reconfigurable 4- and 2-Track: Fault-Tolerant Designs for Mesh-Connected Multicomputers. [Citation Graph (0, 0)][DBLP]
    FTCS, 1996, pp:272-281 [Conf]
  12. Nihar R. Mahapatra, Shantanu Dutt
    Efficient Network-Flow Based Techniques for Dynamic Fault Reconfiguration in FPGAs. [Citation Graph (0, 0)][DBLP]
    FTCS, 1999, pp:122-129 [Conf]
  13. Hasan Arslan, Shantanu Dutt
    An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:208-213 [Conf]
  14. Vishal Suthar, Shantanu Dutt
    High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:78-83 [Conf]
  15. Shantanu Dutt
    New faster Kernighan-Lin-type graph-partitioning algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:370-377 [Conf]
  16. Shantanu Dutt, Wenyong Deng
    VLSI circuit partitioning by cluster-removal using iterative improvement techniques. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:194-200 [Conf]
  17. Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger
    Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:173-177 [Conf]
  18. Shantanu Dutt, Halim Theny
    Partitioning around roadblocks: tackling constraints with intermediate relaxations. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:350-355 [Conf]
  19. Vinay Verma, Shantanu Dutt
    A Search-Based Bump-and-Refit Approach to Incremental Routing for ECO Applications in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:144-0 [Conf]
  20. Ke Zhong, Shantanu Dutt
    Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:254-259 [Conf]
  21. Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suthar
    A network-flow approach to timing-driven incremental placement for ASICs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2006, pp:375-382 [Conf]
  22. Hasan Arslan, Shantanu Dutt
    ROAD : An Order-Impervious Optimal Detailed Router for FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 2003, pp:350-0 [Conf]
  23. Hasan Arslan, Shantanu Dutt
    A Depth-First-Search Controlled Gridless Incremental Routing Algorithm for VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 2004, pp:86-92 [Conf]
  24. Fran Hancheck, Shantanu Dutt
    Design Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:326-331 [Conf]
  25. Shantanu Dutt, Nam Trinh
    Are There Advantages to High-Dimension Architectures? Analysis of k-ary n-Cubes for the Class of Parallel Divide-and-Conquer Algorithms. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1996, pp:398-406 [Conf]
  26. Shantanu Dutt, Nihar R. Mahapatra
    Parallel A* Algorithms and Their Performance on Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPPS, 1993, pp:797-803 [Conf]
  27. Nihar R. Mahapatra, Shantanu Dutt
    Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    IPPS, 1996, pp:881-885 [Conf]
  28. Nihar R. Mahapatra, Shantanu Dutt
    Adaptive Quality Equalizing: High-Performance Load Balancing for Parallel Branch-and-Bound Across Applications and Computing Systems. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:796-800 [Conf]
  29. Shantanu Dutt, Halim Theny
    Partitioning using second-order information and stochastic-gain functions. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:112-117 [Conf]
  30. Nihar R. Mahapatra, Shantanu Dutt
    Scalable Duplicate Pruning Strategies for Parallel A* Graph Search. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:290-297 [Conf]
  31. Shantanu Dutt
    Fast Polylog-Time Reconfiguration of Structurally Fault-Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP]
    SPDP, 1993, pp:762-770 [Conf]
  32. Fran Hanchek, Shantanu Dutt
    Node-Covering Based Defect and Fault Tolerance Methods for Increased Yield in FPGAs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:225-229 [Conf]
  33. Vishal Suthar, Shantanu Dutt
    Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. [Citation Graph (0, 0)][DBLP]
    VTS, 2006, pp:36-43 [Conf]
  34. Nihar R. Mahapatra, Shantanu Dutt
    Random Seeking: A General, Efficient, and Informed Randomized Scheme for Dynamic Load Balancing. [Citation Graph (0, 0)][DBLP]
    Int. J. Found. Comput. Sci., 2000, v:11, n:2, pp:231-246 [Journal]
  35. Shantanu Dutt, John P. Hayes
    Designing Fault-Tolerant System Using Automorphisms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1991, v:12, n:3, pp:249-268 [Journal]
  36. Shantanu Dutt, Nihar R. Mahapatra
    Scalable Load Balancing Strategies for Parallel A* Algorithms. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 1994, v:22, n:3, pp:488-505 [Journal]
  37. Nihar R. Mahapatra, Shantanu Dutt
    Hardware-Efficient and Highly Reconfigurable 4- and 2-Track Fault-Tolerant Designs for Mesh-Connected Arrays. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2001, v:61, n:10, pp:1391-1411 [Journal]
  38. Nihar R. Mahapatra, Shantanu Dutt
    Adaptive Quality Equalizing: High-performance load balancing for parallel branch-and-bound across applications and computing systems. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 2004, v:30, n:5-6, pp:867-881 [Journal]
  39. Shantanu Dutt, Fikri T. Assaad
    Mantissa-Preserving Operations and Robust Algorithm-Based Fault Tolerance for Matrix Computations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1996, v:45, n:4, pp:408-424 [Journal]
  40. Shantanu Dutt, John P. Hayes
    On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:4, pp:490-503 [Journal]
  41. Shantanu Dutt, John P. Hayes
    Subcube Allocation in Hypercube Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1991, v:40, n:3, pp:341-352 [Journal]
  42. Shantanu Dutt, John P. Hayes
    Some Practical Issues in the Design of Fault-Tolerant Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:5, pp:588-598 [Journal]
  43. Shantanu Dutt, Nihar R. Mahapatra
    Node-Covering, Error-Correcting Codes and Multiprocessors with Very High Average Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1997, v:46, n:9, pp:997-1015 [Journal]
  44. Fran Hanchek, Shantanu Dutt
    Methodologies for Tolerating Cell and Interconnect Faults in FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:1, pp:15-33 [Journal]
  45. Shantanu Dutt, Hasan Arslan, Halim Theny
    Partitioning using second-order information and stochastic-gainfunctions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:421-435 [Journal]
  46. Shantanu Dutt, Wenyong Deng
    Probability-based approaches to VLSI circuit partitioning. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:5, pp:534-549 [Journal]
  47. Shantanu Dutt, Wenyong Deng
    Cluster-aware iterative improvement techniques for partitioning large VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:91-121 [Journal]
  48. Shantanu Dutt, Vinay Verma, Hasan Arslan
    A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:4, pp:664-693 [Journal]
  49. Nihar R. Mahapatra, Shantanu Dutt
    Scalable Global and Local Hashing Strategies for Duplicate Pruning in Parallel A* Graph Search. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:7, pp:738-756 [Journal]
  50. Nihar R. Mahapatra, Shantanu Dutt
    An efficient delay-optimal distributed termination detection algorithm. [Citation Graph (0, 0)][DBLP]
    J. Parallel Distrib. Comput., 2007, v:67, n:10, pp:1047-1066 [Journal]
  51. Shantanu Dutt, Fran Hanchek
    REMOD: a new methodology for designing fault-tolerant arithmetic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:34-56 [Journal]

  52. Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure. [Citation Graph (, )][DBLP]


  53. Constraint satisfaction in incremental placement with application to performance optimization under power constraints. [Citation Graph (, )][DBLP]


  54. Selection of Multiple SNPs in Case-Control Association Study Using a Discretized Network Flow Approach. [Citation Graph (, )][DBLP]


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