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Michiel Steyaert: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
    Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:25-30 [Conf]
  2. Carl De Ranter, B. De Muer, Geert Van der Plas, Peter J. Vancorenland, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:11-14 [Conf]
  3. Michiel Steyaert, Peter J. Vancorenland
    CMOS: a paradigm for low power wireless? [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:836-841 [Conf]
  4. Peter J. Vancorenland, Carl De Ranter, Michiel Steyaert, Georges G. E. Gielen
    Optimal RF design using smart evolutionary algorithms. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:7-10 [Conf]
  5. Jan Vandenbussche, K. Uyttenhove, Erik Lauwers, Michiel Steyaert, Georges G. E. Gielen
    Systematic design of a 200 MS/s 8-bit interpolating/averaging A/D converter. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:449-454 [Conf]
  6. Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Michiel Steyaert, Georges G. E. Gielen
    Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:357-361 [Conf]
  7. Jan Crols, Stéphane Donnay, Michiel Steyaert, Georges G. E. Gielen
    A high-level design and optimization tool for analog RF receiver front-ends. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:550-553 [Conf]
  8. Peter J. Vancorenland, Philippe Coppejans, Wouter De Cock, Paul Leroux, Michiel Steyaert
    Optimization of a fully integrated low power CMOS GPS receiver. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:305-308 [Conf]
  9. Peter J. Vancorenland, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    A Layout-Aware Synthesis Methodology for RF Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:358-0 [Conf]
  10. Peter R. Kinget, Michiel Steyaert
    Analogue CMOS VLSI Implementation of Cellular Neural Networks with Continuously Programmable Templates. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:367-370 [Conf]
  11. João Ramos, Kenneth Francken, Georges G. E. Gielen, Michiel Steyaert
    Knowledge- and optimization-based design of RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:629-632 [Conf]
  12. Michiel Steyaert, Jan Crols, S. Gogaert, Willy M. C. Sansen
    Low-voltage Analog CMOS Filter Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1447-1450 [Conf]
  13. Carl De Ranter, Michiel Steyaert
    Design techniques for low power high bandwidth upconversion in CMOS. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:237-242 [Conf]
  14. Marian Verhelst, Wim Vereecken, Michiel Steyaert, Wim Dehaene
    Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:280-285 [Conf]
  15. Carl De Ranter, Geert Van der Plas, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen
    CYCLONE: automated design and layout of RF LC-oscillators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:10, pp:1161-1170 [Journal]
  16. Patrick Reynaert, Koen L. R. Mertens, Michiel Steyaert
    A state-space behavioral model for CMOS class E power amplifiers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:2, pp:132-138 [Journal]
  17. A. Marques, Michiel Steyaert, Willy M. C. Sansen
    Theory of PLL fractional-N frequency synthesizers. [Citation Graph (0, 0)][DBLP]
    Wireless Networks, 1998, v:4, n:1, pp:79-85 [Journal]
  18. Vesselin K. Vassilev, S. Jenei, Guido Groeseneken, R. Venegas, S. Thijs, V. De Heyn, M. Natarajan Iyer, Michiel Steyaert, H. E. Maes
    High frequency characterization and modelling of the parasitic RC performance of two terminal ESD CMOS protection devices. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:7, pp:1011-1020 [Journal]
  19. Vesselin K. Vassilev, S. Thijs, P. L. Segura, P. Wambacq, Paul Leroux, Guido Groeseneken, M. I. Natarajan, H. E. Maes, Michiel Steyaert
    ESD-RF co-design methodology for the state of the art RF-CMOS blocks. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2005, v:45, n:2, pp:255-268 [Journal]
  20. Trent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert
    Simultaneous Multi-Topology Multi-Objective Sizing Across Thousands of Analog Circuit Topologies. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:944-947 [Conf]
  21. Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen
    An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:81-86 [Conf]
  22. Raf Schoofs, Michiel Steyaert, Willy M. C. Sansen
    A 7.5mW, 11-bit continuous-time sigma-delta A/D converter for WLAN applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  23. Massively multi-topology sizing of analog integrated circuits. [Citation Graph (, )][DBLP]


  24. Automated extraction of expert knowledge in analog topology selection and sizing. [Citation Graph (, )][DBLP]


  25. A/D conversion using an Asynchronous Delta-Sigma Modulator and a time-to-digital converter. [Citation Graph (, )][DBLP]


  26. A low-power mixing DAC IR-UWB-receiver. [Citation Graph (, )][DBLP]


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