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Publications of Author

1. Abbas El Gamal, Ivo Bolsens, Andy Broom, Christopher Hamlin, Philippe Magarshack, Zvi Or-Bach, Lawrence T. Pileggi
   Fast, cheap and under control: the next implementation fabric. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:354-355 [Conf]
   
2. Georges G. E. Gielen, Mike Sottak, Mike Murray, Linda Kaye, Maria del Mar Hershenson, Kenneth S. Kundert, Philippe Magarshack, Akria Matsuzawa, Ronald A. Rohrer, Ping Yang
   Panel: When Will the Analog Design Flow Catch Up with Digital Methodology? [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:419- [Conf]
   
3. Philippe Magarshack, Pierre G. Paulin
   System-on-chip beyond the nanometer wall. [Citation Graph (0, 0)][DBLP]
   DAC, 2003, pp:419-424 [Conf]
   
4. G. Singer, Philippe Magarshack, Dennis Buss, F.-C. Hsu, H.-K. Kang
   "The IC nanometer race -- what will it take to win?". [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:77-78 [Conf]
   
5. Georges G. E. Gielen, B. Sorensen, H. Casier, Philippe Magarshack, J. Rodriguez
   Design challenges and emerging EDA solutions in mixed-signal IC design. [Citation Graph (0, 0)][DBLP]
   DATE, 2001, pp:694-695 [Conf]
   
6. Philippe Magarshack
   Design challenges in 45nm and below: DFM, low-power and design for reliability. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:1- [Conf]
   
7. Philippe Magarshack
   Quality of SoC Designs through Quality of the Design Flow: Status and Needs. [Citation Graph (0, 0)][DBLP]
   ISQED, 2001, pp:241-0 [Conf]
   
8. Philippe Magarshack
   Systems-on-chip needs for embedded software development: an industrial perspective. [Citation Graph (0, 0)][DBLP]
   LCTES-SCOPES, 2002, pp:1- [Conf]
   
9. Philippe Magarshack
   SoC's Trends and Challenges going to 0.10µm. [Citation Graph (0, 0)][DBLP]
   MTDT, 2002, pp:- [Conf]
   
10. Philippe Magarshack
    Invited Keynote: Building Yield into Systems-on-Chips for Nanometer Technologies. [Citation Graph (0, 0)][DBLP]
    VTS, 2003, pp:4- [Conf]
    
11. Philippe Magarshack
    Improving SoC Design Quality through a Reproducible Design Flow. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:1, pp:76-83 [Journal]
    
12. Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack
    Guest Editors' Introduction: Design for Yield and Reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:177-182 [Journal]
    
13. Marco Casale-Rossi, Andrzej J. Strojwas, Robert C. Aitken, Antun Domic, Carlo Guardiani, Philippe Magarshack, Douglas Pattullo, Joseph Sawicki
    DFM/DFY: should you trust the surgeon or the family doctor? [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:439-442 [Conf]
    
14. 
    3-D stacked die: now or future? [Citation Graph (, )][DBLP]
    
    
15. 
    Low-Power Design Solutions forWireless Multimedia SoCs. [Citation Graph (, )][DBLP]