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Publications of Author

1. Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
   A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:625-631 [Conf]
   
2. Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer
   Software Accelerated Functional Fault Simulation for Data-Path Architectures. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:333-338 [Conf]
   
3. Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski
   Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:1285-1294 [Conf]
   
4. Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski
   Realizing High Test Quality Goals with Smart Test Resource Usage. [Citation Graph (0, 0)][DBLP]
   ITC, 2004, pp:525-533 [Conf]
   
5. Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski
   Logic BIST for large industrial designs: real issues and case studies. [Citation Graph (0, 0)][DBLP]
   ITC, 1999, pp:358-367 [Conf]
   
6. Mark Kassab, Janusz Rajski, Jerzy Tyszer
   Hierarchical Functional-Fault Simulation for High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
   ITC, 1995, pp:596-605 [Conf]
   
7. Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski
   Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. [Citation Graph (0, 0)][DBLP]
   ITC, 2003, pp:1211-1220 [Conf]
   
8. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian
   Embedded Deterministic Test for Low-Cost Manufacturing Test. [Citation Graph (0, 0)][DBLP]
   ITC, 2002, pp:301-310 [Conf]
   
9. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
   Embedded Deterministic Test for Low-Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:58-66 [Journal]
   
10. Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee
    Embedded deterministic test. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:5, pp:776-792 [Journal]
    
11. Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski
    Test Generation in the Presence of Timing Exceptions and Constraints. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:688-693 [Conf]
    
12. 
    Test Generation for Designs with On-Chip Clock Generators. [Citation Graph (, )][DBLP]
    
    
13. 
    X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. [Citation Graph (, )][DBLP]