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N. P. van der Meijs: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. P. J. H. Elias, N. P. van der Meijs
    Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:764-769 [Conf]
  2. A. J. van Genderen, N. P. van der Meijs
    Using Articulation Nodes to Improve the Efficiency of Finite-Element based Resistance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:758-763 [Conf]
  3. N. P. van der Meijs, A. J. van Genderen
    An Efficient Finite Element Method for Submicron IC Capacitance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:678-681 [Conf]
  4. N. P. van der Meijs, A. J. van Genderen
    Delayed Frontal Solution for Finite-Element Based Resistance Extraction. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:273-278 [Conf]
  5. Eelco Schrik, N. P. van der Meijs
    Combined BEM/FEM substrate resistance modeling. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:771-776 [Conf]
  6. Giuseppe S. Garcea, N. P. van der Meijs, Kees-Jan van der Kolk, Ralph H. J. M. Otten
    Statistically Aware Buffer Planning. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1402-1403 [Conf]
  7. A. J. Dammers, N. P. van der Meijs
    Virtual screening: a step towards a sparse partial inductance matrix. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:445-452 [Conf]
  8. Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. J. M. Otten
    Simultaneous Analytic Area and Power Optimization for Repeater Insertion. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:568-573 [Conf]
  9. A. J. van Genderen, N. P. van der Meijs
    Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:764-769 [Conf]
  10. N. P. van der Meijs, T. Smedes
    Accurate interconnect modeling: towards multi-million transistor chips as microwave circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:244-251 [Conf]
  11. Eelco Schrik, Patrick Dewilde, N. P. van der Meijs
    Theoretical and practical validation of combined BEM/FEM substrate resistance modeling. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:10-15 [Conf]
  12. T. Smedes, N. P. van der Meijs, A. J. van Genderen
    Extraction of circuit models for substrate cross-talk. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:199-206 [Conf]
  13. Frederik Beeftink, A. J. van Genderen, N. P. van der Meijs
    Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:360-365 [Conf]

  14. Cartesian multipole based numerical integration for 3D capacitance extraction. [Citation Graph (, )][DBLP]


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