|
Search the dblp DataBase
Ti-Yen Yen:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- Wen-Jong Fang, Allen C.-H. Wu, Ti-Yen Yen
A Real-Time RTL Engineering-Change Method Supporting On-Line Debugging for Logic-Emulation Applications. [Citation Graph (0, 0)][DBLP] DAC, 1997, pp:101-106 [Conf]
- Ti-Yen Yen, Wayne Wolf
Communication synthesis for distributed embedded systems. [Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:288-294 [Conf]
- Ti-Yen Yen, Wayne Wolf
Optimal Scheduling of Finite-State Machines. [Citation Graph (0, 0)][DBLP] ICCD, 1993, pp:366-369 [Conf]
- Ti-Yen Yen, Wayne Wolf
Performance estimation for real-time distributed embedded systems. [Citation Graph (0, 0)][DBLP] ICCD, 1995, pp:64-71 [Conf]
- Ti-Yen Yen, Wayne Wolf
Sensitivity-driven co-synthesis of distributed embedded systems. [Citation Graph (0, 0)][DBLP] ISSS, 1995, pp:4-9 [Conf]
- Ti-Yen Yen, Alex Ishii, Albert E. Casavant, Wayne Wolf
Efficient Algorithms for Interface Timing Verification. [Citation Graph (0, 0)][DBLP] Formal Methods in System Design, 1998, v:12, n:3, pp:241-265 [Journal]
- Ti-Yen Yen, Wayne Wolf
Performance Estimation for Real-Time Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP] IEEE Trans. Parallel Distrib. Syst., 1998, v:9, n:11, pp:1125-1136 [Journal]
- Ti-Yen Yen, Wayne Wolf
An efficient graph algorithm for FSM scheduling. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:98-112 [Journal]
Efficient algorithms for interface timing verification. [Citation Graph (, )][DBLP]
Search in 0.001secs, Finished in 0.002secs
|