SCEAS

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Rajiv Jain: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

Yaw Fann, Minjoong Rim, Rajiv Jain
Global Scheduling for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP]
DAC, 1994, pp:542-546 [Conf]
Rajiv Jain, Kayhan Küçükçakar, Mitch J. Mlinar, Alice C. Parker
Experience with ADAM Synthesis System. [Citation Graph (0, 0)][DBLP]
DAC, 1989, pp:56-61 [Conf]
Rajiv Jain, Ashutosh Mujumdar, Alok Sharma, Hueymin Wang
Empirical Evaluation of Some High-Level Synthesis Scheduling Heuristics. [Citation Graph (0, 0)][DBLP]
DAC, 1991, pp:686-689 [Conf]
Rajiv Jain, Alice C. Parker, Nohbyung Park
Predicting Area-Time Tradeoffs for Pipelined Design. [Citation Graph (0, 0)][DBLP]
DAC, 1987, pp:35-41 [Conf]
Rajiv Jain, Alice C. Parker, Nohbyung Park
Module Selection for Pipelined Synthesis. [Citation Graph (0, 0)][DBLP]
DAC, 1988, pp:542-547 [Conf]
Minjoong Rim, Rajiv Jain
Representing Conditional Branches for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP]
DAC, 1992, pp:106-111 [Conf]
Minjoong Rim, Rajiv Jain, Renato De Leone
Optimal Allocation and Binding in High-Level Synthesis. [Citation Graph (0, 0)][DBLP]
DAC, 1992, pp:120-123 [Conf]
Alok Sharma, Rajiv Jain
InSyn: Integrated Scheduling for DSP Applications. [Citation Graph (0, 0)][DBLP]
DAC, 1993, pp:349-354 [Conf]
Alok Sharma, Rajiv Jain
Estimating Architectural Resources and Performance for High-Level Synthesis Applications. [Citation Graph (0, 0)][DBLP]
DAC, 1993, pp:355-360 [Conf]
Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
Behavioral Synthesis of Testable Designs. [Citation Graph (0, 0)][DBLP]
FTCS, 1994, pp:436-445 [Conf]
Ashutosh Mujumdar, Kewal K. Saluja, Rajiv Jain
Incorporating Testability Considerations in High-Level Systhesis. [Citation Graph (0, 0)][DBLP]
FTCS, 1992, pp:272-279 [Conf]
Hao Zheng, Kewal K. Saluja, Rajiv Jain
Test application time reduction for scan based sequential circuits. [Citation Graph (0, 0)][DBLP]
Great Lakes Symposium on VLSI, 1995, pp:188-191 [Conf]
Rajiv Jain
MOSP: Module Selection for Pipelined Designs with Multi-Cycle Operations. [Citation Graph (0, 0)][DBLP]
ICCAD, 1990, pp:212-215 [Conf]
Wing Hang Wong, Rajiv Jain
PARAS: system-level concurrent partitioning and scheduling. [Citation Graph (0, 0)][DBLP]
ICCAD, 1995, pp:440-445 [Conf]
Minjoong Rim, Rajiv Jain
Estimating Lower-Bound Performance of Schedules Using a Relaxation Technique. [Citation Graph (0, 0)][DBLP]
ICCD, 1992, pp:290-294 [Conf]
Alok Sharma, Rajiv Jain
Register Estimation from Behavioral Specifications. [Citation Graph (0, 0)][DBLP]
ICCD, 1994, pp:576-580 [Conf]
Meera Balakrishnan, Rajiv Jain, C. S. Raghavendra
On Array Storage for Conflict-Free Memory Access for Parallel Processors. [Citation Graph (0, 0)][DBLP]
ICPP (1), 1988, pp:103-107 [Conf]
Minjoong Rim, Rajiv Jain
Valid Transformations: A New Class of Loop Transformations. [Citation Graph (0, 0)][DBLP]
ICPP, 1994, pp:20-23 [Conf]
Minjoong Rim, Rajiv Jain
Estimating Performance Characteristics of Loop Transformations. [Citation Graph (0, 0)][DBLP]
ISCAS, 1994, pp:249-252 [Conf]
Anil Nori, Rajiv Jain
Composite Applications: Process Based Application Development. [Citation Graph (0, 0)][DBLP]
TES, 2002, pp:48-53 [Conf]
Ashutosh Majumdar, Minjoong Rim, Rajiv Jain, Renato De Leone
BINET: An Algorithm for Solving the Binding Problem. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1994, pp:163-168 [Conf]
R. K. Aditham, Rajiv Jain, Murali Srinivasan
Interest Based Collaboration Framework. [Citation Graph (0, 0)][DBLP]
WETICE, 1997, pp:75-81 [Conf]
Anil Nori, Chandar Venkatraman, Rajiv Jain
Defining the Next Generation e-Business Platform: A Discussion of the Asers eBusiness Platform. [Citation Graph (0, 0)][DBLP]
IEEE Data Eng. Bull., 2001, v:24, n:1, pp:18-22 [Journal]
Rajiv Jain, Alice C. Parker, Nohbyung Park
Predicting system-level area and delay for pipelined and nonpipelined designs. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:8, pp:955-965 [Journal]
Ashutosh Mujumdar, Rajiv Jain, Kewal K. Saluja
Incorporating performance and testability constraints during binding in high-level synthesis. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:10, pp:1212-1225 [Journal]
Minjoong Rim, Rajiv Jain
Lower-bound performance estimation for the high-level synthesis scheduling problem. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:4, pp:451-458 [Journal]
Minjoong Rim, Rajiv Jain
Valid Transformations: A New Class of Loop Transformations for High-Level Synthesis and Pipelined Scheduling Applications. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:4, pp:399-410 [Journal]
Minjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone
Optimal and heuristic algorithms for solving the binding problem. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1994, v:2, n:2, pp:211-225 [Journal]
Minjoong Rim, Yaw Fann, Rajiv Jain
Global scheduling with code-motions for high-level synthesis applications. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1995, v:3, n:3, pp:379-392 [Journal]

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The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP