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Publications of Author

1. Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
   Memory Segmentation to Exploit Sleep Mode Operation. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:36-41 [Conf]
   
2. Amir H. Farrahi, Majid Sarrafzadeh
   FPGA Technology Mapping for Power Minimization. [Citation Graph (0, 0)][DBLP]
   FPL, 1994, pp:66-77 [Conf]
   
3. Amir H. Farrahi, Majid Sarrafzadeh
   System partitioning to maximize sleep time. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:452-455 [Conf]
   
4. Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh
   Activity-driven clock design for low power circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1995, pp:62-65 [Conf]
   
5. Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh
   Quality of EDA CAD Tools: Definitions, Metrics and Directions. [Citation Graph (0, 0)][DBLP]
   ISQED, 2000, pp:395-406 [Conf]
   
6. Amir H. Farrahi
   Estimation and removal or routing congestion (discussion session). [Citation Graph (0, 0)][DBLP]
   SLIP, 2000, pp:149- [Conf]
   
7. Amir H. Farrahi, D. T. Lee, Majid Sarrafzadeh
   Two-Way and Multiway Partitioning of a Set of Intervals for Clique-Width Maximization. [Citation Graph (0, 0)][DBLP]
   Algorithmica, 1999, v:23, n:3, pp:187-210 [Journal]
   
8. Wei-Liang Lin, Amir H. Farrahi, Majid Sarrafzadeh
   On the Power of Logic Resynthesis. [Citation Graph (0, 0)][DBLP]
   SIAM J. Comput., 2000, v:29, n:4, pp:1257-1289 [Journal]
   
9. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
   Activity-driven clock design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal]
   
10. Amir H. Farrahi, Majid Sarrafzadeh
    Complexity of the lookup-table minimization problem for FPGA technology mapping. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:11, pp:1319-1332 [Journal]