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Gustavo E. Téllez: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Amir H. Farrahi, Gustavo E. Téllez, Majid Sarrafzadeh
    Memory Segmentation to Exploit Sleep Mode Operation. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:36-41 [Conf]
  2. Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
    Unification of Budgeting and Placement. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:758-761 [Conf]
  3. Gustavo E. Téllez, Amir H. Farrahi, Majid Sarrafzadeh
    Activity-driven clock design for low power circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:62-65 [Conf]
  4. Gustavo E. Téllez, Majid Sarrafzadeh
    Clock period constrained minimal buffer insertion in clock trees. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:219-223 [Conf]
  5. Gustavo E. Téllez, Majid Sarrafzadeh
    On Rectilinear Distance-Preserving Trees. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:163-166 [Conf]
  6. Fook-Luen Heng, Zhan Chen, Gustavo E. Téllez
    A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation. [Citation Graph (0, 0)][DBLP]
    ISPD, 1997, pp:116-121 [Conf]
  7. Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh
    Activity-driven clock design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:6, pp:705-714 [Journal]
  8. Majid Sarrafzadeh, David A. Knol, Gustavo E. Téllez
    A delay budgeting algorithm ensuring maximum flexibility in placement. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:11, pp:1332-1341 [Journal]
  9. Gustavo E. Téllez, Majid Sarrafzadeh
    Minimal buffer insertion in clock trees with skew and slew rate constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:4, pp:333-342 [Journal]

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