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John P. Fishburn: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. John P. Fishburn
    A Depth-Decreasing Heuristic for Combinational Logic: Or How To Convert a Ripple-Carry Adder Into A Carry-Lookahead Adder Or Anything in-between. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:361-364 [Conf]
  2. John P. Fishburn
    LATTIS: An Iterative Speedup Heuristic for Mapped Logic. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:488-491 [Conf]
  3. Dwight D. Hill, John P. Fishburn, Mary Diane Palmer Leland
    Effective use of virtual grid compaction in macro-module generators. [Citation Graph (0, 0)][DBLP]
    DAC, 1985, pp:777-780 [Conf]
  4. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
    Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:467-470 [Conf]
  5. John P. Fishburn
    Optimization-based calibration of a static timing analyzer to path delay measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:186-189 [Conf]
  6. Kung-Chao Chu, John P. Fishburn, Peter Honeyman, Y. Edmund Lien
    Vdd - A VLSI Design Database System. [Citation Graph (0, 0)][DBLP]
    Engineering Design Applications, 1983, pp:25-37 [Conf]
  7. Raphael A. Finkel, John P. Fishburn
    Parallelism in Alpha-Beta Search. [Citation Graph (0, 0)][DBLP]
    Artif. Intell., 1982, v:19, n:1, pp:89-106 [Journal]
  8. John P. Fishburn
    Solving a system of difference constraints with variables restricted to a finite set. [Citation Graph (0, 0)][DBLP]
    Inf. Process. Lett., 2002, v:82, n:3, pp:143-144 [Journal]
  9. John P. Fishburn
    Clock Skew Optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:7, pp:945-951 [Journal]
  10. John P. Fishburn, Raphael A. Finkel
    Quotient Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1982, v:31, n:4, pp:288-295 [Journal]
  11. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Interconnect synthesis without wire tapering. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:90-104 [Journal]
  12. Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay
    Correction to "interconnect synthesis without wire tapering". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:4, pp:497-497 [Journal]
  13. Kung-Chao Chu, John P. Fishburn, Peter Honeyman, Y. Edmund Lien
    A Database-Driven VLSI Design System. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:180-187 [Journal]
  14. Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn
    Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:2, pp:173-182 [Journal]

  15. Shaping a VLSI wire to minimize Elmore delay. [Citation Graph (, )][DBLP]


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