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Publications of Author

1. Elof Frank, Salil Raje, Majid Sarrafzadeh
   Constrained Register Allocation in Bus Architectures. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:170-175 [Conf]
   
2. Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
   Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP]
   DAC, 2004, pp:741-746 [Conf]
   
3. Jun Dong Cho, Salil Raje, Majid Sarrafzadeh
   Approximation Algorithm on Multi-Way Maxcut Partitioning. [Citation Graph (0, 0)][DBLP]
   ESA, 1994, pp:148-158 [Conf]
   
4. André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica
   What is the right model for programming and using modern FPGAs? [Citation Graph (0, 0)][DBLP]
   FPGA, 2004, pp:119- [Conf]
   
5. Navaratnasothie Selvakkumaran, Abhishek Ranjan, Salil Raje, George Karypis
   Multi-resource aware partitioning algorithms for FPGAs with heterogeneous resources. [Citation Graph (0, 0)][DBLP]
   FPGA, 2004, pp:253- [Conf]
   
6. Salil Raje, Reinaldo A. Bergamaschi
   Generalized resource sharing. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1997, pp:326-332 [Conf]
   
7. Maogang Wang, Abhishek Ranjan, Salil Raje
   Multi-Million Gate FPGA Physical Design Challenges. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:891-899 [Conf]
   
8. Salil Raje, Majid Sarrafzadeh
   GEM: A Geometric Algorithm for Scheduling. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1993, pp:1991-1994 [Conf]
   
9. Majid Sarrafzadeh, Salil Raje
   Scheduling with multiple voltages under resource constraints. [Citation Graph (0, 0)][DBLP]
   ISCAS (1), 1999, pp:350-353 [Conf]
   
10. Salil Raje, Majid Sarrafzadeh
    Variable voltage scheduling. [Citation Graph (0, 0)][DBLP]
    ISLPD, 1995, pp:9-14 [Conf]
    
11. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
    Overcoming wireload model uncertainty during physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:182-189 [Conf]
    
12. Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh
    Innovate or perish: FPGA physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2004, pp:148-155 [Conf]
    
13. Reinaldo A. Bergamaschi, Salil Raje
    Observable Time Windows: Verifying High-Level Synthesis Results. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:2, pp:40-50 [Journal]
    
14. Salil Raje, Majid Sarrafzadeh
    Scheduling with multiple voltages. [Citation Graph (0, 0)][DBLP]
    Integration, 1997, v:23, n:1, pp:37-59 [Journal]
    
15. Jun Dong Cho, Salil Raje, Majid Sarrafzadeh
    Fast Approximation Algorithms on Maxcut, k-Coloring, and k-Color Ordering vor VLSI Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1998, v:47, n:11, pp:1253-1266 [Journal]
    
16. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
    An analysis of the wire-load model uncertainty problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:23-31 [Journal]
    
17. Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan
    Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:82-100 [Journal]