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Paul D. Franzon: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ajay Dholakia, T. M. Lee, Donald L. Bitzer, Mladen A. Vouk, L. Wang, Paul D. Franzon
    An efficient table-driven decoder for one-half rate convolutional codes. [Citation Graph (0, 0)][DBLP]
    ACM Southeast Regional Conference, 1992, pp:116-123 [Conf]
  2. B. E. Duewer, J. M. Wilson, D. A. Winick, Paul D. Franzon
    MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications. [Citation Graph (0, 0)][DBLP]
    ARVLSI, 1999, pp:369-377 [Conf]
  3. Paul D. Franzon, Mark Basel, Aki Fujimara, Sharad Mehrotra, Ron Preston, Robin C. Sarma, Marty Walker
    Parasitic Extraction Accuracy - How Much is Enough? [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:429- [Conf]
  4. Paul D. Franzon, Slobodan Simovich, Michael Steer, Mark Basel, Sharad Mehrotra, Tom Mills
    Tools to Aid in Wiring Rule Generation for High Speed Interconnects. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:466-471 [Conf]
  5. Sharad Mehrotra, Paul D. Franzon, Wentai Liu
    Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:36-40 [Conf]
  6. Sharad Mehrotra, Paul D. Franzon, Michael Steer
    Performance Driven Global Routing and Wiring Rule Generation for High Speed PCBs and MCMs. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:381-387 [Conf]
  7. Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte
    Dynamically Programmable Cache Evaluation and Virtualization. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:246- [Conf]
  8. Liang Zhang, Wentai Liu, Rizwan Bashirullah, John Wilson, Paul D. Franzon
    Simplified delay design guidelines for on-chip global interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:29-32 [Conf]
  9. Andreas Kuehlmann, Robert W. Dutton, Paul D. Franzon, Seth Copen Goldstein, Philip Luekes, Eric Parker, Thomas N. Theis
    Will Nanotechnology Change the Way We Design and Verify Systems? (Panel). [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:174- [Conf]
  10. Todd A. Cook, Paul D. Franzon, Edwin A. Harcourt, Thomas K. Miller III
    System-Level Specification of Instruction Sets. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:552-557 [Conf]
  11. Mir Azam, Paul D. Franzon, Wentai Liu
    Low power data processing by elimination of redundant computations. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1997, pp:259-264 [Conf]
  12. Liang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
    Driver pre-emphasis techniques for on-chip global buses. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2005, pp:186-191 [Conf]
  13. Numan Sadi Dogan, Paul D. Franzon, Wentai Liu
    Impact of an SoC Research Project on Microelectronics Education: A Case Study. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:33-34 [Conf]
  14. Toby Schaffer, Andy Stanaski, Alan Glaser, Paul D. Franzon
    The NCSU Cadence Design Kit for IC Fabrication through MOSIS. [Citation Graph (0, 0)][DBLP]
    MSE, 1999, pp:88-89 [Conf]
  15. Paul D. Franzon, Robert J. Evans
    A Multichip Module Design Process for Notebook Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 1993, v:26, n:4, pp:41-49 [Journal]
  16. W. Rhett Davis, John Wilson, Stephen Mick, Jian Xu, Hao Hua, Christopher Mineo, Ambarish M. Sule, Michael Steer, Paul D. Franzon
    Demystifying 3D ICs: The Pros and Cons of Going Vertical. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:6, pp:498-510 [Journal]
  17. Monther Aldwairi, Thomas M. Conte, Paul D. Franzon
    Configurable string matching hardware for speeding up intrusion detection. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:1, pp:99-107 [Journal]
  18. J. A. Palmer, James F. Mulling, Brian Dessent, Edward Grant, Jeffrey W. Eischen, Alexei Gruverman, A. I. Kingon, Paul D. Franzon
    The Design, Fabrication, and Characterization of Millimeter Scale Motors for Miniature Direct Drive Robots. [Citation Graph (0, 0)][DBLP]
    ICRA, 2004, pp:4668-4673 [Conf]
  19. Meeta Yadav, Ashwini Venkatachaliah, Paul D. Franzon
    Hardware Architecture of a Parallel Pattern Matching Engine. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1369-1372 [Conf]
  20. Liang Zhang, J. M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon
    Voltage-Mode Driver Preemphasis Technique For On-Chip Global Buses. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:231-236 [Journal]

  21. Design and CAD for 3D integrated circuits. [Citation Graph (, )][DBLP]


  22. Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study. [Citation Graph (, )][DBLP]


  23. Creating 3D specific systems: Architecture, design and CAD. [Citation Graph (, )][DBLP]


  24. A low power 3D integrated FFT engine using hypercube memory division. [Citation Graph (, )][DBLP]


  25. Comparative analysis of two 3D integration implementations of a SAR processor. [Citation Graph (, )][DBLP]


  26. Technology impact analysis for 3D TCAM. [Citation Graph (, )][DBLP]


  27. Junction-level thermal extraction and simulation of 3DICs. [Citation Graph (, )][DBLP]


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