Search the dblp DataBase

Publications of Author

1. Serge Gaiotti, Michel Dagenais, Nicholas C. Rumin
   Worst-case Delay Estimation of Transistor Groups. [Citation Graph (0, 0)][DBLP]
   DAC, 1989, pp:491-495 [Conf]
   
2. Michel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin
   The McBOOLE logic minimizer. [Citation Graph (0, 0)][DBLP]
   DAC, 1985, pp:667-673 [Conf]
   
3. Abdolreza Nabavi-Lishi, Nicholas C. Rumin
   Delay and bus current evaluation in CMOS logic circuits. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1992, pp:198-203 [Conf]
   
4. Min Ma, Mourad Oulmane, Nicholas C. Rumin
   Explicit delay metric for interconnect optimization. [Citation Graph (0, 0)][DBLP]
   ISCAS (3), 2005, pp:2453-2456 [Conf]
   
5. Abdolreza Nabavi-Lishi, Nicholas C. Rumin
   Inverter-based Models for Current Analysis of CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP]
   ISCAS, 1994, pp:13-16 [Conf]
   
6. Yvon Savaria, Vinod K. Agarwal, Nicholas C. Rumin, Jeremiah F. Hayes
   A Design for Machines with Built-In Tolerance to Soft Errors. [Citation Graph (0, 0)][DBLP]
   ITC, 1984, pp:649-659 [Conf]
   
7. Jean Paul Caisso, Eduard Cerny, Nicholas C. Rumin
   A recursive technique for computing delays in series-parallel MOS transistor circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:5, pp:589-595 [Journal]
   
8. Eduard Cerny, John P. Hayes, Nicholas C. Rumin
   Accuracy of magnitude-class calculations in switch-level modeling. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:443-452 [Journal]
   
9. Michel Dagenais, Vinod K. Agarwal, Nicholas C. Rumin
   McBOOLE: A New Procedure for Exact Logic Minimization. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:1, pp:229-238 [Journal]
   
10. Michel Dagenais, Serge Gaiotti, Nicholas C. Rumin
    Transistor-level estimation of worst-case delays in MOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:3, pp:384-395 [Journal]
    
11. Michel Dagenais, Nicholas C. Rumin
    On the calculation of optimal clocking parameters in synchronous circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:3, pp:268-278 [Journal]
    
12. Mohamed Hafed, Mourad Oulmane, Nicholas C. Rumin
    Delay and current estimation in a CMOS inverter with an RC load. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:1, pp:80-89 [Journal]
    
13. Denis Martin, Nicholas C. Rumin
    Delay prediction from resistance-capacitance models of general MOS circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:7, pp:997-1003 [Journal]
    
14. Abdolreza Nabavi-Lishi, Nicholas C. Rumin
    Inverter models of CMOS gates for supply current and delay evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1271-1279 [Journal]