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Publications of Author

1. Daniel Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
   System-level exploration with SpecSyn. [Citation Graph (0, 0)][DBLP]
   DAC, 1998, pp:812-817 [Conf]
   
2. Sanjiv Narayan, Daniel Gajski
   Protocol Generation for Communication Channels. [Citation Graph (0, 0)][DBLP]
   DAC, 1994, pp:547-551 [Conf]
   
3. Sanjiv Narayan, Daniel Gajski
   Interfacing Incompatible Protocols Using Interface Process Generation. [Citation Graph (0, 0)][DBLP]
   DAC, 1995, pp:468-473 [Conf]
   
4. Sanjiv Narayan, Daniel Gajski
   Synthesis of System-Level Bus Interfaces. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:395-399 [Conf]
   
5. Daniel Gajski, Frank Vahid, Sanjiv Narayan
   A System-Design Methodology: Executable-Specification Refinement. [Citation Graph (0, 0)][DBLP]
   EDAC-ETC-EUROASIC, 1994, pp:458-463 [Conf]
   
6. Sanjiv Narayan, Frank Vahid, Daniel Gajski
   System Specification and Synthesis with the SpecCharts Language. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1991, pp:266-269 [Conf]
   
7. G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja
   Graph Transformations for Improved Tree Height Reduction. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2003, pp:474-479 [Conf]
   
8. Sanjiv Narayan, Frank Vahid, Daniel D. Gajski
   System Specification with the SpecCharts Language. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1992, v:9, n:4, pp:6-13 [Journal]
   
9. Frank Vahid, Sanjiv Narayan, Daniel D. Gajski
   SpecCharts: a VHDL front-end for embedded systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:6, pp:694-706 [Journal]
   
10. En-Shou Chang, Daniel Gajski, Sanjiv Narayan
    An optimal clock period selection method based on slack minimization criteria. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1996, v:1, n:3, pp:352-370 [Journal]
    
11. Daniel D. Gajski, Sanjiv Narayan, L. Ramachandran, Frank Vahid, P. Fung
    System design methodologies: aiming at the 100 h design cycle. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:1, pp:70-82 [Journal]
    
12. Daniel D. Gajski, Frank Vahid, Sanjiv Narayan, Jie Gong
    SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:1, pp:84-100 [Journal]
    
13. 
    A transformation for integrating VHDL behavioral specification with synthesis and software generation. [Citation Graph (, )][DBLP]
    
    
14. 
    100-hour design cycle: a test case. [Citation Graph (, )][DBLP]