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Publications of Author

1. Kaushik Gala, David Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
   Inductance 101: Analysis and Design Issues. [Citation Graph (0, 0)][DBLP]
   DAC, 2001, pp:329-334 [Conf]
   
2. Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Brian Young, Junfeng Wang, David Blaauw
   On-chip inductance modeling and analysis. [Citation Graph (0, 0)][DBLP]
   DAC, 2000, pp:63-68 [Conf]
   
3. David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang
   On-chip inductance modeling. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2000, pp:75-80 [Conf]
   
4. Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
   A precorrected-FFT method for simulating on-chip inductance. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2002, pp:221-227 [Conf]
   
5. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
   Fast Analysis and Optimization of Power/Ground Networks. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2000, pp:477-480 [Conf]
   
6. Haitian Hu, David Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
   Table look-up based compact modeling for on-chip interconnect timing and noise analysis. [Citation Graph (0, 0)][DBLP]
   ISCAS (4), 2003, pp:668-671 [Conf]
   
7. Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
   Worst case clock skew under power supply variations. [Citation Graph (0, 0)][DBLP]
   Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:22-28 [Conf]
   
8. Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
   Fast on-chip inductance simulation using a precorrected-FFT method. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:1, pp:49-66 [Journal]
   
9. Haihua Su, Kaushik Gala, Sachin S. Sapatnekar
   Analysis and optimization of structured power/ground networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1533-1544 [Journal]
   
10. Kaushik Gala, David Blaauw, Vladimir Zolotov, P. M. Vaidya, A. Joshi
    Inductance model and analysis methodology for high-speed on-chip interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:730-745 [Journal]