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Rajesh Garg: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi
    A design approach for radiation-hard digital electronics. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:773-778 [Conf]
  2. Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri
    A PLA based asynchronous micropipelining approach for subthreshold circuit design. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:419-424 [Conf]
  3. Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri
    A design flow to optimize circuit delay by using standard cells and PLAs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:217-222 [Conf]
  4. Rajesh Garg, Sunil P. Khatri
    Generalized buffering of PTL logic stages using Boolean division. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  5. Jeff Cobb, Rajesh Garg, Sunil P. Khatri
    A methodology for interconnect dimension determination. [Citation Graph (0, 0)][DBLP]
    ISPD, 2007, pp:189-195 [Conf]

  6. Efficient analytical determination of the SEU-induced pulse shape. [Citation Graph (, )][DBLP]


  7. A fast, analytical estimator for the SEU-induced pulse width in combinational designs. [Citation Graph (, )][DBLP]


  8. A Single-supply True Voltage Level Shifter. [Citation Graph (, )][DBLP]


  9. A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. [Citation Graph (, )][DBLP]


  10. A lithography-friendly structured ASIC design approach. [Citation Graph (, )][DBLP]


  11. Pipelined network of PLA based circuit design. [Citation Graph (, )][DBLP]


  12. A robust, fast pulsed flip-flop design. [Citation Graph (, )][DBLP]


  13. Low power and high performance sram design using bank-based selective forward body bias. [Citation Graph (, )][DBLP]


  14. On the Improvement of Statistical Static Timing Analysis. [Citation Graph (, )][DBLP]


  15. CMOS Comparators for High-Speed and Low-Power Applications. [Citation Graph (, )][DBLP]


  16. A novel, highly SEU tolerant digital circuit design approach. [Citation Graph (, )][DBLP]


  17. Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). [Citation Graph (, )][DBLP]


  18. Design and implementation of a sub-threshold BFSK transmitter. [Citation Graph (, )][DBLP]


  19. SEU hardened clock regeneration circuits. [Citation Graph (, )][DBLP]


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