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Vikram Jandhyala: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dipanjan Gope, Swagato Chakraborty, Vikram Jandhyala
    A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:794-799 [Conf]
  2. Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala
    DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. [Citation Graph (0, 0)][DBLP]
    DAC, 2005, pp:159-162 [Conf]
  3. Vikram Jandhyala, Scott Savage, J. Eric Bracken, Zoltan J. Cendes
    Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface Meshes. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:543-548 [Conf]
  4. Chuanyi Yang, Swagato Chakraborty, Dipanjan Gope, Vikram Jandhyala
    A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:1053-1056 [Conf]
  5. Vikram Jandhyala, Yong Wang, Dipanjan Gope, C.-J. Richard Shi
    Coupled Electromagnetic-Circuit Simulation of Arbitrarily-Shaped Conducting Structures Using Triangular Meshes. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:38-42 [Conf]
  6. Pavel V. Nikitin, Vikram Jandhyala, Daniel White, Nathan Champagne, John D. Rockway, C.-J. Richard Shi, Chuanyi Yang, Yong Wang, Gong Ouyang, Rob Sharpe, John W. Rockway
    Modeling and Simulation of Circuit-Electromagnetic Effects in Electronic Design Flow. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:244-249 [Conf]
  7. Vikram Jandhyala, Yasuo Kuga, David J. Allstot, C.-J. Richard Shi
    Bridging Circuits and Electromagnetics in a Curriculum Aimed at Microelectronic Analog and Microwave Simulation and Design. [Citation Graph (0, 0)][DBLP]
    MSE, 2005, pp:45-46 [Conf]
  8. Indranil Chowdhury, Vikram Jandhyala
    Multilevel multipole and local operators for potentials of the form r-lambda. [Citation Graph (0, 0)][DBLP]
    Appl. Math. Lett., 2005, v:18, n:10, pp:1184-1189 [Journal]
  9. Dipanjan Gope, Vikram Jandhyala
    Oct-tree-based multilevel low-rank decomposition algorithm for rapid 3-D parasitic extraction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:11, pp:1575-1580 [Journal]
  10. Hao Gang Wang, Chi Hou Chan, Leung Tsang, Vikram Jandhyala
    On sampling algorithms in multilevel QR factorization method for magnetoquasistatic analysis of integrated circuits over multilayered lossy substrates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:9, pp:1777-1792 [Journal]
  11. Dipanjan Gope, Albert E. Ruehli, Vikram Jandhyala
    Speeding Up PEEC Partial Inductance Computations Using a QR-Based Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:60-68 [Journal]

  12. Statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach. [Citation Graph (, )][DBLP]

  13. Active-passive co-synthesis of multi-GigaHertz radio frequency circuits with broadband parametric macromodels of on-chip passives. [Citation Graph (, )][DBLP]

  14. Accurate statistical analysis of a differential low noise amplifier using a combined SPICE-field solver approach. [Citation Graph (, )][DBLP]

  15. Efficient hierarchical discretization of off-chip power delivery network geometries for 2.5D electrical analysis. [Citation Graph (, )][DBLP]

  16. Towards Active-Passive Co-synthesis of Multi-gigaHertz Radio Frequency Circuits. [Citation Graph (, )][DBLP]

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