The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Kurt Antreich: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich
    Improved Methods for Worst-Case Analysis and Optimization Incorporating Operating Tolerances. [Citation Graph (0, 0)][DBLP]
    DAC, 1993, pp:142-147 [Conf]
  2. Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
    Path Hashing to Accelerate Delay Fault Simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:522-526 [Conf]
  3. Alfred Kölbl, James H. Kukula, Kurt Antreich, Robert F. Damiano
    Handling special constructs in symbolic simulation. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:105-110 [Conf]
  4. Bernhard Rohfleisch, Bernd Wurth, Kurt Antreich
    Logic Clause Analysis for Delay Optimization. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:668-672 [Conf]
  5. Frank Schenkel, Michael Pronath, Stephan Zizala, Robert Schwencker, Helmut E. Graeb, Kurt Antreich
    Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:858-863 [Conf]
  6. Guido Stehr, Helmut E. Graeb, Kurt Antreich
    Performance trade-off analysis of analog circuits by normal-boundary intersection. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:958-963 [Conf]
  7. Bernd Wurth, Klaus Eckl, Kurt Antreich
    Functional Multiple-Output Decomposition: Theory and an Implicit Algorithm. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:54-59 [Conf]
  8. Michael Pronath, Helmut E. Graeb, Kurt Antreich
    A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:78-83 [Conf]
  9. Robert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich
    Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:323-327 [Conf]
  10. Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
    The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2000, pp:42-47 [Conf]
  11. Peter A. Krauss, Kurt Antreich
    Application of Fault Parallelism to the Automatic Test Pattern Generation for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
    Parallel Computer Architectures, 1993, pp:234-245 [Conf]
  12. Kurt Antreich, Franz J. Rammig, Wolfgang Rosenstiel, Detlef Schmid, Klaus Waldschmidt
    DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    GI Jahrestagung, 1997, pp:93-101 [Conf]
  13. Kurt Antreich, Helmut E. Graeb
    Circuit Optimization Driven by Worst-Case Distances. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:166-169 [Conf]
  14. Helmut E. Graeb, Stephan Zizala, Josef Eckmueller, Kurt Antreich
    The Sizing Rules Method for Analog Integrated Circuit Design. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2001, pp:343-349 [Conf]
  15. Manfred Henftling, Hannes C. Wittmann, Kurt Antreich
    A single-path-oriented fault-effect propagation in digital circuits considering multiple-path sensitization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:304-309 [Conf]
  16. Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
    Design based analog testing by Characteristic Observation Inference. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:620-626 [Conf]
  17. Guido Stehr, Helmut E. Graeb, Kurt Antreich
    Analog performance space exploration by Fourier-Motzkin elimination with application to hierarchical sizing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:847-854 [Conf]
  18. Guido Stehr, Michael Pronath, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
    Initial Sizing of Analog Integrated Circuits by Centering Within Topology-Given Implicit Specification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:241-246 [Conf]
  19. Henning Spruth, Frank M. Johannes, Kurt Antreich
    PHIroute: A Parallel Hierarchical Sea-of-Gates Router. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:487-490 [Conf]
  20. Kurt Antreich, Franz J. Rammig, Wolfgang Rosenstiel, Detlef Schmid, Klaus Waldschmidt
    DFG-Schwerpunktprogramm: Entwurf und Entwurfsmethodik eingebetteter Systeme. [Citation Graph (0, 0)][DBLP]
    Inform., Forsch. Entwickl., 1997, v:12, n:4, pp:220-223 [Journal]
  21. Kurt Antreich, Helmut E. Graeb, Claudia U. Wieser
    Circuit analysis and optimization driven by worst-case distances. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:1, pp:57-71 [Journal]
  22. Kurt Antreich, Michael H. Schulz
    Accelerated Fault Simulation and Fault Grading in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:5, pp:704-712 [Journal]
  23. Konrad Doll, Frank M. Johannes, Kurt Antreich
    Iterative placement improvement by network flow methods. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:10, pp:1189-1200 [Journal]
  24. Jürgen M. Kleinhans, Georg Sigl, Frank M. Johannes, Kurt Antreich
    GORDIAN: VLSI placement by quadratic programming and slicing optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:3, pp:356-365 [Journal]
  25. Walter M. Lindermeir, Helmut E. Graeb, Kurt Antreich
    Analog testing by characteristic observation inference. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1353-1368 [Journal]
  26. Paul Tafertshofer, Andreas Ganz, Kurt Antreich
    IGRAINE-an Implication GRaph-bAsed engINE for fast implication, justification, and propagation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:8, pp:907-927 [Journal]
  27. Bernd Wurth, Ulf Schlichtmann, Klaus Eckl, Kurt Antreich
    Functional multiple-output decomposition with application to technology mapping for lookup table-based FPGAs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1999, v:4, n:3, pp:313-350 [Journal]

  28. A formal non-heuristic ATPG approach. [Citation Graph (, )][DBLP]


  29. A new power estimation technique with application to decomposition of Boolean functions for low power. [Citation Graph (, )][DBLP]


  30. An accurate model for ambiguity delay simulation. [Citation Graph (, )][DBLP]


Search in 0.018secs, Finished in 0.020secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002