The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Werner Geurts: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Werner Geurts, Francky Catthoor, Hugo De Man
    Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing. [Citation Graph (0, 0)][DBLP]
    DAC, 1992, pp:124-127 [Conf]
  2. Stefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man
    Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:597-602 [Conf]
  3. Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens
    Chess: retargetable code generation for embedded DSP processors. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:85-102 [Conf]
  4. F. Depuydt, Werner Geurts, Gert Goossens, Hugo De Man
    Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:490-494 [Conf]
  5. Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man
    Solving large scale assignment problems in high-level synthesis by approximative quadratic programming. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:19-24 [Conf]
  6. Werner Geurts, Francky Catthoor, Hugo De Man
    Quadratic zero-one programming based synthesis of application specific data paths. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1993, pp:522-525 [Conf]
  7. Werner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man
    Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. [Citation Graph (0, 0)][DBLP]
    VLSI, 1991, pp:193-202 [Conf]
  8. Werner Geurts, Francky Catthoor, Hugo De Man
    Quadratic zero-one programming-based synthesis of application-specific data paths. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:1, pp:1-11 [Journal]
  9. Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens
    Processor modeling and code selection for retargetable compilation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:277-307 [Journal]

Search in 0.025secs, Finished in 0.025secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002