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Pei-Ning Guo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Pei-Ning Guo, Chung-Kuan Cheng, Takeshi Yoshimura
An O-Tree Representation of Non-Slicing Floorplan and Its Applications. [Citation Graph (0, 0)][DBLP]
DAC, 1999, pp:268-273 [Conf] - Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
Cluster Refinement for Block Placement. [Citation Graph (0, 0)][DBLP]
DAC, 1997, pp:762-765 [Conf] - Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
A physical retiming algorithm for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
FPGA, 2003, pp:247- [Conf] - Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
Rectilinear block placement using sequence-pair. [Citation Graph (0, 0)][DBLP]
ISPD, 1998, pp:173-178 [Conf] - Pei-Ning Guo, Toshihiko Takahashi, Chung-Kuan Cheng, Takeshi Yoshimura
Floorplanning using a tree representation. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:2, pp:281-289 [Journal] - Jin Xu, Pei-Ning Guo, Chung-Kuan Cheng
Sequence-pair approach for rectilinear module placement. [Citation Graph (0, 0)][DBLP]
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:4, pp:484-493 [Journal]
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