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Publications of Author

1. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
   Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability. [Citation Graph (0, 0)][DBLP]
   Asian Test Symposium, 2005, pp:404-409 [Conf]
   
2. Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, Kaushik Roy
   Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. [Citation Graph (0, 0)][DBLP]
   DAC, 2006, pp:971-976 [Conf]
   
3. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
   A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2006, pp:619-624 [Conf]
   
4. Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
   A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2005, pp:287-292 [Conf]
   
5. Swaroop Ghosh, Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy
   Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2006, pp:31-36 [Conf]
   
6. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
   Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling. [Citation Graph (0, 0)][DBLP]
   DATE, 2007, pp:1532-1537 [Conf]
   
7. Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy
   Tolerance to Small Delay Defects by Adaptive Clock Stretching. [Citation Graph (0, 0)][DBLP]
   IOLTS, 2007, pp:244-252 [Conf]
   
8. Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
   Low-Power and testable circuit synthesis using Shannon decomposition. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Design Autom. Electr. Syst., 2007, v:12, n:4, pp:- [Journal]
   
9. 
   Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching. [Citation Graph (, )][DBLP]
   
   
10. 
    A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking. [Citation Graph (, )][DBLP]
    
    
11. 
    O²C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors. [Citation Graph (, )][DBLP]
    
    
12. 
    Coping with Variations through System-Level Design. [Citation Graph (, )][DBLP]