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K. Parthasarathy: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Debabrata Ghosh, S. K. Nandy, P. Sadayappan, K. Parthasarathy
Architectural Synthesis of Performance-Driven Multipliers with Accumulator Interleaving. [Citation Graph (0, 0)][DBLP]
DAC, 1993, pp:303-307 [Conf] - Debabrata Ghosh, S. K. Nandy, K. Parthasarathy
TWTXBB: A Low Latency, High Throughput Multiplier Architecture Using a New 4 --> 2 Compressor. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1994, pp:77-82 [Conf] - Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1993, pp:341-346 [Conf] - G. N. Rathna, S. K. Nandy, K. Parthasarathy
A Methodology for Architecture Synthesis of Cascaded IIR Filters on TLU FPGAs. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1994, pp:225-228 [Conf] - M. K. Sridhar, R. Srinath, K. Parthasarathy
On the direct parallel solution of systems of linear equations: New algorithms and systolic structures. [Citation Graph (0, 0)][DBLP]
Inf. Sci., 1987, v:43, n:1-2, pp:25-53 [Journal]
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