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Avaneendra Gupta: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Avaneendra Gupta, John P. Hayes
    CLIP: An Optimizing Layout Generator for Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:452-455 [Conf]
  2. Avaneendra Gupta, John P. Hayes
    Width minimization of two-dimensional CMOS cells using integer programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:660-667 [Conf]
  3. Avaneendra Gupta, John P. Hayes
    Optimal 2-D cell layout with integrated transistor folding. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:128-135 [Conf]
  4. Avaneendra Gupta, John P. Hayes
    A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:15-20 [Conf]
  5. Avaneendra Gupta, John P. Hayes
    Near-Optimum Hierarchical Layout Synthesis of Two-Dimensional CMOS Cells. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:453-459 [Conf]
  6. Avaneendra Gupta, John P. Hayes
    CLIP: integer-programming-based optimal layout synthesis of 2D CMOS cells. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2000, v:5, n:3, pp:510-547 [Journal]

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