Search the dblp DataBase

Publications of Author

1. Subodh Gupta, Farid N. Najm
   Power Macromodeling for High Level Power Estimation. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:365-370 [Conf]
   
2. Subodh Gupta, Farid N. Najm
   Power macro-models for DSP blocks with application to high-level synthesis. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1999, pp:103-105 [Conf]
   
3. Subodh Gupta, Farid N. Najm
   Energy-per-cycle estimation at RTL. [Citation Graph (0, 0)][DBLP]
   ISLPED, 1999, pp:121-126 [Conf]
   
4. Subodh Gupta, Farid N. Najm
   Analytical models for RTL power estimation of combinational andsequential circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:7, pp:808-814 [Journal]
   
5. Subodh Gupta, Farid N. Najm
   Power modeling for high-level power estimation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2000, v:8, n:1, pp:18-29 [Journal]
   
6. Subodh Gupta, Farid N. Najm
   Energy and peak-current per-cycle estimation at RTL. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. VLSI Syst., 2003, v:11, n:4, pp:525-537 [Journal]
   
7. 
   Clock power reduction for virtex-5 FPGAs. [Citation Graph (, )][DBLP]