Search the dblp DataBase

Publications of Author

1. Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha
   Efficient fingerprint-based user authentication for embedded systems. [Citation Graph (0, 0)][DBLP]
   DAC, 2005, pp:244-247 [Conf]
   
2. Pallav Gupta, Niraj K. Jha
   An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:974-979 [Conf]
   
3. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
   Test generation for combinational quantum cellular automata (QCA) circuits. [Citation Graph (0, 0)][DBLP]
   DATE, 2006, pp:311-316 [Conf]
   
4. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
   Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. [Citation Graph (0, 0)][DBLP]
   DATE, 2004, pp:904-909 [Conf]
   
5. Pallav Gupta, Lin Zhong, Niraj K. Jha
   A High-level Interconnect Power Model for Design Space Exploration. [Citation Graph (0, 0)][DBLP]
   ICCAD, 2003, pp:551-559 [Conf]
   
6. Pallav Gupta, Rui Zhang, Niraj K. Jha
   An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. [Citation Graph (0, 0)][DBLP]
   ICCD, 2004, pp:540-543 [Conf]
   
7. Rui Zhang, Pallav Gupta, Niraj K. Jha
   Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 2005, pp:229-234 [Conf]
   
8. Pallav Gupta, Abhinav Agrawal, Niraj K. Jha
   An Algorithm for Synthesis of Reversible Logic Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:11, pp:2317-2330 [Journal]
   
9. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha
   Threshold network synthesis and optimization and its application to nanotechnologies. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:1, pp:107-118 [Journal]
   
10. Pallav Gupta, Niraj K. Jha, Loganathan Lingappan
    A Test Generation Framework for Quantum Cellular Automata Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:1, pp:24-36 [Journal]