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Publications of Author

1. Mohankumar Guruswamy, Robert L. Maziasz, Daniel Dulitz, Srilata Raman, Venkat Chiluvuri, Andrea Fernandez, Larry G. Jones
   CELLERITY: A Fully Automatic Layout Synthesis System for Standard Cell Libraries. [Citation Graph (0, 0)][DBLP]
   DAC, 1997, pp:327-332 [Conf]
   
2. Larry G. Jones
   Accelerating Switch-Level Simulation by Function Caching. [Citation Graph (0, 0)][DBLP]
   DAC, 1991, pp:211-214 [Conf]
   
3. Larry G. Jones
   Zero Delay versus Positive Delay in an Incremental Switch-Level Simulator. [Citation Graph (0, 0)][DBLP]
   DAC, 1992, pp:424-427 [Conf]
   
4. Alexey Glebov, David Blaauw, Larry G. Jones
   Transistor reordering for low power CMOS gates using an SP-BDD representation. [Citation Graph (0, 0)][DBLP]
   ISLPD, 1995, pp:161-166 [Conf]
   
5. Larry G. Jones, Janos Simon
   Hierarchical VLSI Design Systems Based on Attribute Grammars. [Citation Graph (0, 0)][DBLP]
   POPL, 1986, pp:58-69 [Conf]
   
6. Larry G. Jones
   Fast batch incremental netlist compilation hierarchical schematics. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:7, pp:922-931 [Journal]
   
7. Larry G. Jones
   An incremental zero/integer delay switch-level simulation environment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1131-1139 [Journal]
   
8. Larry G. Jones, David Blaauw
   A cache-based method for accelerating switch-level simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1994, v:13, n:2, pp:211-218 [Journal]
   
9. Larry G. Jones
   Efficient Evaluation of Circular Attribute Grammars. [Citation Graph (0, 0)][DBLP]
   ACM Trans. Program. Lang. Syst., 1990, v:12, n:3, pp:429-462 [Journal]
   
10. 
    Fast power loss calculation for digital static CMOS circuits. [Citation Graph (, )][DBLP]
    
    
11. 
    A delay driven FPGA placement algorithm. [Citation Graph (, )][DBLP]