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Gert Goossens: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gert Goossens, Joos Vandewalle, Hugo De Man
    Loop Optimization in Register-Transfer Scheduling for DSP-Systems. [Citation Graph (0, 0)][DBLP]
    DAC, 1989, pp:826-831 [Conf]
  2. Marco Cornero, Filip Thoen, Gert Goossens, Francesco Curatelli
    Software Synthesis for real-time information processing systems. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:260-279 [Conf]
  3. Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens
    Chess: retargetable code generation for embedded DSP processors. [Citation Graph (0, 0)][DBLP]
    Code Generation for Embedded Processors, 1994, pp:85-102 [Conf]
  4. Koen Schoofs, Gert Goossens, Hugo De Man
    Signal Type Optimisation in the Design of Time-Multiplexed DSP Architectures. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:502-506 [Conf]
  5. F. Depuydt, Werner Geurts, Gert Goossens, Hugo De Man
    Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization. [Citation Graph (0, 0)][DBLP]
    EDAC-ETC-EUROASIC, 1994, pp:490-494 [Conf]
  6. F. Depuydt, Gert Goossens, Hugo De Man
    Clustering Techniques for Register Optimization During Scheduling Preprocessing. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:280-283 [Conf]
  7. Gert Goossens, Ivo Bolsens, Bill Lin, Francky Catthoor
    Design of heterogeneous ICs for mobile and personal communication systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:524-531 [Conf]
  8. Peter Vanbekbergen, Francky Catthoor, Gert Goossens, Hugo De Man
    Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:184-187 [Conf]
  9. Peter Vanbekbergen, Bill Lin, Gert Goossens, Hugo De Man
    A generalized state assignment theory for transformation on signal transition graphs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1992, pp:112-117 [Conf]
  10. Augusli Kifli, R. De Wulf, J. Zegers, Gert Goossens, Paul Six, Hugo De Man
    Flag/Condition Handling and Branch Assignment for Large Microcoded Controllers. [Citation Graph (0, 0)][DBLP]
    Synthesis for Control Dominated Circuits, 1992, pp:61-71 [Conf]
  11. Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man
    Real-time multi-tasking in software synthesis for information processing systems. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:48-53 [Conf]
  12. Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man
    Software Synthesis for Real-Time Information Processing Systems. [Citation Graph (0, 0)][DBLP]
    Workshop on Languages, Compilers, & Tools for Real-Time Systems, 1995, pp:60-69 [Conf]
  13. Gert Goossens, Jan M. Rabaey, Joos Vandewalle, Hugo De Man
    An efficient microcode compiler for application specific DSP processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:9, pp:925-937 [Journal]
  14. Stefaan Note, Francky Catthoor, Gert Goossens, Hugo De Man
    Combined hardware selection and pipelining in high-performance data-path design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:4, pp:413-423 [Journal]
  15. Peter Vanbekbergen, Gert Goossens, Francky Catthoor, Hugo De Man
    Optimized synthesis of asynchronous control circuits from graph-theoretic specifications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1426-1438 [Journal]
  16. Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens
    Processor modeling and code selection for retargetable compilation. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2001, v:6, n:3, pp:277-307 [Journal]
  17. Ahmed Amine Jerraya, Gert Goossens
    Guest Editorial Introduction to the Special Issue on the Eighth IEEE International Symposium on System Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:57-58 [Journal]

  18. Multi-thread graph: a system model for real-time embedded software synthesis. [Citation Graph (, )][DBLP]


  19. Open-ended system for high-level synthesis of flexible signal processors. [Citation Graph (, )][DBLP]


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