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Soha Hassoun: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Soha Hassoun
    Critical path analysis using a dynamically bounded delay model. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:260-265 [Conf]
  2. Soha Hassoun, Carl Ebeling
    Architectural Retiming: Pipelining Latency-Constrained Circuts. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:708-713 [Conf]
  3. Murali Kudlugi, Soha Hassoun, Charles Selvidge, Duaine Pryor
    A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:623-628 [Conf]
  4. Brian Swahn, Soha Hassoun
    Gate sizing: finFETs vs 32nm bulk MOSFETs. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:528-531 [Conf]
  5. Soha Hassoun, Eduardo Calvillo-Gámez, Christopher Cromer
    Verifying Clock Schedules in the Presence of Cross Talk. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:346-351 [Conf]
  6. Soha Hassoun, Charles J. Alpert, Meera Thiagarajan
    Optimal buffered routing path constructions for single and multiple clock domain systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:247-253 [Conf]
  7. Soha Hassoun, Carl Ebeling
    Using precomputation in architecture and logic resynthesis. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:316-323 [Conf]
  8. Soha Hassoun, Carolyn McCreary
    Regularity extraction via clan-based structural circuit decomposition. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:414-419 [Conf]
  9. Brian Swahn, Soha Hassoun
    Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2003, pp:58-65 [Conf]
  10. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    ISCA, 1987, pp:189-196 [Conf]
  11. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
    Architecture of a Message-Driven Processor. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:337-344 [Conf]
  12. Soha Hassoun
    Optimal use of 2-phase transparent latches in buffered maze routing. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2003, pp:688-691 [Conf]
  13. Brian Swahn, Soha Hassoun
    METS: A Metric for Electro-Thermal Sensitivity, and Its Application To FinFETs. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:121-126 [Conf]
  14. Soha Hassoun
    Fine Grain Incremental Rescheduling Via Architectural Retiming. [Citation Graph (0, 0)][DBLP]
    ISSS, 1998, pp:158-163 [Conf]
  15. Soha Hassoun, Soheila Bana
    Practices for Recruiting and Retaining Graduate Women Students in Computer Science and Engineering. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:106-0 [Conf]
  16. Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw
    Robust SAT-Based Search Algorithm for Leakage Power Reduction. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:167-177 [Conf]
  17. Kevin Bolding, Sen-Ching Cheung, Sung-Eun Choi, Carl Ebeling, Soha Hassoun, Ton Anh Ngo, Robert Wille
    The chaos router chip: design and implementation of an adaptive router. [Citation Graph (0, 0)][DBLP]
    VLSI, 1993, pp:311-320 [Conf]
  18. Soha Hassoun, Geert Janssen
    First CADathlon Programming Contest held at 2002 ICCAD. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:104-107 [Journal]
  19. Soha Hassoun, Yong-Bin Kim, Fabrizio Lombardi
    Guest Editors' Introduction: Clockless VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:6, pp:5-8 [Journal]
  20. Sani R. Nassif, Soha Hassoun
    Guest Editors' Introduction: On-Chip Power Distribution Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:3, pp:5-6 [Journal]
  21. Soha Hassoun, Charles J. Alpert
    Optimal path routing in single- and multiple-clock domain systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:11, pp:1580-1588 [Journal]
  22. Soha Hassoun, Christopher Cromer, Eduardo Calvillo-Gámez
    Static timing analysis for level-clocked circuits in the presence of crosstalk. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:9, pp:1270-1277 [Journal]
  23. Soha Hassoun, Steven M. Nowick, Leon Stok
    Guest Editorial. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2003, v:22, n:6, pp:662-664 [Journal]
  24. Soha Hassoun, Murali Kudlugi, Duaine Pryor, Charles Selvidge
    A transaction-based unified architecture for simulation and emulation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:2, pp:278-287 [Journal]

  25. Joint DAC/IWBDA special session engineering biology: fundamentals and applications. [Citation Graph (, )][DBLP]


  26. Evolving soft robotic locomotion in PhysX. [Citation Graph (, )][DBLP]


  27. An algorithm for identifying dominant-edge metabolic pathways. [Citation Graph (, )][DBLP]


  28. Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. [Citation Graph (, )][DBLP]


  29. System-level comparison of power delivery design for 2D and 3D ICs. [Citation Graph (, )][DBLP]


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