The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Anmol Mathur: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    An Efficient Assertion Checker for Combinational Properties. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:734-739 [Conf]
  2. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:611-614 [Conf]
  3. Anmol Mathur, Sanjeev Saluja
    Improved Merging of Datapath Operators using Information Content and Required Precision Analysis. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:462-467 [Conf]
  4. Anmol Mathur, K. C. Chen, C. L. Liu
    Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1995, pp:118-124 [Conf]
  5. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    Efficient equivalence checking of multi-phase designs using retiming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1998, pp:557-562 [Conf]
  6. Alfred Koelbl, Yuan Lu, Anmol Mathur
    Embedded tutorial: formal equivalence checking between system-level models and RTL. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2005, pp:965-971 [Conf]
  7. Anmol Mathur, K. C. Chen, C. L. Liu
    Re-engineering of timing constrained placements for regular architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:485-490 [Conf]
  8. Anmol Mathur, C. L. Liu
    Compression-relaxation: a new approach to performance driven placement for regular architectures. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:130-136 [Conf]
  9. G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja
    Graph Transformations for Improved Tree Height Reduction. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2003, pp:474-479 [Conf]
  10. Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
    Sequential Equivalence Checking. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2006, pp:18-19 [Conf]
  11. Anmol Mathur, Edward M. Reingold
    Generalized Kraft's Inequality and Discrete k-Modal Search. [Citation Graph (0, 0)][DBLP]
    SIAM J. Comput., 1996, v:25, n:2, pp:420-447 [Journal]
  12. Anmol Mathur, C. L. Liu
    Timing-driven placement for regular architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:597-608 [Journal]
  13. Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
    Efficient equivalence checking of multi-phase designs using phase abstraction and retiming. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:600-625 [Journal]
  14. Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
    Rate analysis for embedded systems. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:408-436 [Journal]
  15. Anmol Mathur, Venkat Krishnaswamy
    Design for Verification in System-level Models and RTL. [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:193-198 [Conf]

  16. Non-cycle-accurate sequential equivalence checking. [Citation Graph (, )][DBLP]


  17. RATAN: A tool for rate analysis and rate constraint debugging for embedded systems. [Citation Graph (, )][DBLP]


  18. Power Reduction Techniques and Flows at RTL and System Level. [Citation Graph (, )][DBLP]


  19. Functional Equivalence Verification Tools in High-Level Synthesis Flows. [Citation Graph (, )][DBLP]


Search in 0.062secs, Finished in 0.063secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002