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## Search the dblp DataBase
Anmol Mathur:
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## Publications of Author- Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
**An Efficient Assertion Checker for Combinational Properties.**[Citation Graph (0, 0)][DBLP] DAC, 1997, pp:734-739 [Conf] - Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
**An Implicit Algorithm for Finding Steady States and its Application to FSM Verification.**[Citation Graph (0, 0)][DBLP] DAC, 1998, pp:611-614 [Conf] - Anmol Mathur, Sanjeev Saluja
**Improved Merging of Datapath Operators using Information Content and Required Precision Analysis.**[Citation Graph (0, 0)][DBLP] DAC, 2001, pp:462-467 [Conf] - Anmol Mathur, K. C. Chen, C. L. Liu
**Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.**[Citation Graph (0, 0)][DBLP] FPGA, 1995, pp:118-124 [Conf] - Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
**Efficient equivalence checking of multi-phase designs using retiming.**[Citation Graph (0, 0)][DBLP] ICCAD, 1998, pp:557-562 [Conf] - Alfred Koelbl, Yuan Lu, Anmol Mathur
**Embedded tutorial: formal equivalence checking between system-level models and RTL.**[Citation Graph (0, 0)][DBLP] ICCAD, 2005, pp:965-971 [Conf] - Anmol Mathur, K. C. Chen, C. L. Liu
**Re-engineering of timing constrained placements for regular architectures.**[Citation Graph (0, 0)][DBLP] ICCAD, 1995, pp:485-490 [Conf] - Anmol Mathur, C. L. Liu
**Compression-relaxation: a new approach to performance driven placement for regular architectures.**[Citation Graph (0, 0)][DBLP] ICCAD, 1994, pp:130-136 [Conf] - G. N. Mangalam, Sanjiv Narayan, Paul van Besouw, LaNae J. Avra, Anmol Mathur, Sanjeev Saluja
**Graph Transformations for Improved Tree Height Reduction.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2003, pp:474-479 [Conf] - Anmol Mathur, Masahiro Fujita, M. Balakrishnan, Raj S. Mitra
**Sequential Equivalence Checking.**[Citation Graph (0, 0)][DBLP] VLSI Design, 2006, pp:18-19 [Conf] - Anmol Mathur, Edward M. Reingold
**Generalized Kraft's Inequality and Discrete**[Citation Graph (0, 0)][DBLP]*k*-Modal Search. SIAM J. Comput., 1996, v:25, n:2, pp:420-447 [Journal] - Anmol Mathur, C. L. Liu
**Timing-driven placement for regular architectures.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:6, pp:597-608 [Journal] - Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee
**Efficient equivalence checking of multi-phase designs using phase abstraction and retiming.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:4, pp:600-625 [Journal] - Anmol Mathur, Ali Dasdan, Rajesh K. Gupta
**Rate analysis for embedded systems.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:408-436 [Journal] - Anmol Mathur, Venkat Krishnaswamy
**Design for Verification in System-level Models and RTL.**[Citation Graph (0, 0)][DBLP] DAC, 2007, pp:193-198 [Conf] **Non-cycle-accurate sequential equivalence checking.**[Citation Graph (, )][DBLP]**RATAN: A tool for rate analysis and rate constraint debugging for embedded systems.**[Citation Graph (, )][DBLP]**Power Reduction Techniques and Flows at RTL and System Level.**[Citation Graph (, )][DBLP]**Functional Equivalence Verification Tools in High-Level Synthesis Flows.**[Citation Graph (, )][DBLP]
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