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Vladimir Stojanovic: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hamid Hatamkhani, Frank Lambrecht, Vladimir Stojanovic, Chih-Kong Ken Yang
    Power-centric design of high-speed I/Os. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:867-872 [Conf]
  2. Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss
    A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:705-708 [Conf]
  3. Robert W. Brodersen, Mark Horowitz, Dejan Markovic, Borivoje Nikolic, Vladimir Stojanovic
    Methods for true power minimization. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2002, pp:35-42 [Conf]
  4. Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa
    A unified approach in the analysis of latches and flip-flops for low-power systems. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:227-232 [Conf]
  5. Vladimir Stojanovic
    High-Speed Serial Links: Design Trends and Challenges, invited. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:514- [Conf]
  6. Amir Amirkhany, Ali-Azam Abbasfar, Vladimir Stojanovic, Mark A. Horowitz
    Analog Multi-Tone Signaling for High-Speed Backplane Electrical Links. [Citation Graph (0, 0)][DBLP]
    GLOBECOM, 2006, pp:- [Conf]

  7. Yield-driven iterative robust circuit optimization algorithm. [Citation Graph (, )][DBLP]


  8. Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. [Citation Graph (, )][DBLP]


  9. Low-Complexity Pattern-Eliminating Codes for ISI-Limited Channels. [Citation Graph (, )][DBLP]


  10. Practical Limits of Multi-Tone Signaling Over High-Speed Backplane Electrical Links. [Citation Graph (, )][DBLP]


  11. Statistical Simulator for Block Coded Channels with Long Residual Interference. [Citation Graph (, )][DBLP]


  12. Equalized interconnects for on-chip networks: modeling and optimization framework. [Citation Graph (, )][DBLP]


  13. Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example. [Citation Graph (, )][DBLP]


  14. Integrated circuit design with NEM relays. [Citation Graph (, )][DBLP]


  15. Designing multi-socket systems using silicon photonics. [Citation Graph (, )][DBLP]


  16. Re-architecting DRAM memory systems with monolithically integrated silicon photonics. [Citation Graph (, )][DBLP]


  17. A Modeling and exploration framework for interconnect network design in the nanometer era. [Citation Graph (, )][DBLP]


  18. Silicon-photonic clos networks for global on-chip communication. [Citation Graph (, )][DBLP]


  19. Characterization of Equalized and Repeated Interconnects for NoC Applications. [Citation Graph (, )][DBLP]


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