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Mustafa Celik :
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Zhijiang He , Mustafa Celik , Lawrence T. Pileggi SPIE: Sparse Partial Inductance Extraction. [Citation Graph (0, 0)][DBLP ] DAC, 1997, pp:137-140 [Conf ] Yi-Chang Lu , Mustafa Celik , Tak Young , Lawrence T. Pileggi Min/max On-Chip Inductance Models and Delay Metrics. [Citation Graph (0, 0)][DBLP ] DAC, 2001, pp:341-346 [Conf ] Emrah Acar , Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1999, pp:60-63 [Conf ] Mustafa Celik , Andreas C. Cangellaris A general dispersive multiconductor transmission line model for interconnect simulation in SPICE. [Citation Graph (0, 0)][DBLP ] ICCAD, 1996, pp:563-568 [Conf ] Xin Li , Jiayong Le , Mustafa Celik , Lawrence T. Pileggi Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations. [Citation Graph (0, 0)][DBLP ] ICCAD, 2005, pp:844-851 [Conf ] Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi PRIMA: passive reduced-order interconnect macromodeling algorithm. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:58-65 [Conf ] Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi Practical considerations for passive reduction of RLC circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1999, pp:214-220 [Conf ] Mustafa Celik , O. Ocali , Mehmet Ali Tan , Abdullah Atalar Improving AWE Accuracy Using Multipoint Padé Approximation. [Citation Graph (0, 0)][DBLP ] ISCAS, 1994, pp:379-382 [Conf ] Ayhan A. Mutlu , Kelvin J. Le , Mustafa Celik , Dar-sun Tsien , Garry Shyu , Long-Ching Yeh An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization. [Citation Graph (0, 0)][DBLP ] ISQED, 2007, pp:677-684 [Conf ] Mustafa Celik , Andreas C. Cangellaris Simulation of multiconductor transmission lines using Krylov subspace order-reduction techniques. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:5, pp:485-496 [Journal ] Mustafa Celik , Lawrence T. Pileggi Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:3, pp:293-300 [Journal ] Altan Odabasioglu , Mustafa Celik , Lawrence T. Pileggi PRIMA: passive reduced-order interconnect macromodeling algorithm. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:645-654 [Journal ] A parametric approach for handling local variation effects in timing analysis. [Citation Graph (, )][DBLP ] Parametric analysis to determine accurate interconnect extraction corners for design performance. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs