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Hans T. Heineken: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
    CAD at the Design-Manufacturing Interface. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:321-326 [Conf]
  2. Hans T. Heineken, Wojciech Maly
    Performance - Manufacturability Tradeoffs in IC Design. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:563-0 [Conf]
  3. Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
    Design-Manufacturing Interface: Part I - Vision. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:550-556 [Conf]
  4. Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
    Design-Manufacturing Interface: Part II - Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:557-562 [Conf]
  5. Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
    Detection of Yield Trends. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:62-68 [Conf]
  6. Hans T. Heineken, Wojciech Maly
    Interconnect yield model for manufacturability prediction in synthesis of standard cell based designs. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:368-373 [Conf]
  7. Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
    Design for manufacturability in submicron domain. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:690-697 [Conf]
  8. Hans T. Heineken, Jitendra Khare
    Test Strategies For a 40Gbps Framer SoC. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:758-763 [Conf]
  9. Jitendra Khare, Hans T. Heineken, M. d'Abreu
    Cost Trade-Offs in System On Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:178-184 [Conf]
  10. Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d'Abreu
    Maximizing Wafer Productivity Through Layout Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:192-197 [Conf]
  11. Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken
    Manufacturability and Testability Oriented Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:185-191 [Conf]

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