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Jitendra Khare: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
    CAD at the Design-Manufacturing Interface. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:321-326 [Conf]
  2. Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
    Design-Manufacturing Interface: Part I - Vision. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:550-556 [Conf]
  3. Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
    Design-Manufacturing Interface: Part II - Applications. [Citation Graph (0, 0)][DBLP]
    DATE, 1998, pp:557-562 [Conf]
  4. Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
    Design for manufacturability in submicron domain. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:690-697 [Conf]
  5. John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly
    Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. [Citation Graph (0, 0)][DBLP]
    ITC, 2001, pp:258-267 [Conf]
  6. Hans T. Heineken, Jitendra Khare
    Test Strategies For a 40Gbps Framer SoC. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:758-763 [Conf]
  7. Jitendra Khare
    DFM - A Fabless Perspective. [Citation Graph (0, 0)][DBLP]
    ITC, 2003, pp:1317- [Conf]
  8. Jitendra Khare
    Memory Yield Improvement - SoC Design Perspective. [Citation Graph (0, 0)][DBLP]
    ITC, 2004, pp:1445- [Conf]
  9. Jitendra Khare, Wojciech Maly
    Inductive Contamination Analysis (ICA) with SRAM Application. [Citation Graph (0, 0)][DBLP]
    ITC, 1995, pp:552-560 [Conf]
  10. Jitendra Khare, Hans T. Heineken, M. d'Abreu
    Cost Trade-Offs in System On Chip Designs. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:178-184 [Conf]
  11. Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
    Testability-oriented channel routing. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:208-213 [Conf]
  12. Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, Saghir A. Shaikh, M. d'Abreu
    Maximizing Wafer Productivity Through Layout Optimization. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:192-197 [Conf]
  13. Saghir A. Shaikh, Jitendra Khare, Hans T. Heineken
    Manufacturability and Testability Oriented Synthesis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:185-191 [Conf]
  14. A. Bommireddy, Jitendra Khare, Saghir A. Shaikh, S.-T. Su
    Test and Debug of Networking SoCs: A Case Study. [Citation Graph (0, 0)][DBLP]
    VTS, 2000, pp:121-126 [Conf]
  15. John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare
    Enabling Embedded Memory Diagnosis via Test Response Compression. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:292-298 [Conf]
  16. Jitendra Khare, Wojciech Maly, Nathan Tiday
    Fault characterization of standard cell libraries using inductive contamination. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:405-413 [Conf]

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