SCEAS

The SCEAS System

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Pranab K. Nag: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
CAD at the Design-Manufacturing Interface. [Citation Graph (0, 0)][DBLP]
DAC, 1997, pp:321-326 [Conf]
Wojciech Maly, Pranab K. Nag, Hans T. Heineken, Jitendra Khare
Design-Manufacturing Interface: Part I - Vision. [Citation Graph (0, 0)][DBLP]
DATE, 1998, pp:550-556 [Conf]
Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Hans T. Heineken, Jitendra Khare, P. Simon
Design-Manufacturing Interface: Part II - Applications. [Citation Graph (0, 0)][DBLP]
DATE, 1998, pp:557-562 [Conf]
Wojciech Maly, Hans T. Heineken, Jitendra Khare, Pranab K. Nag
Design for manufacturability in submicron domain. [Citation Graph (0, 0)][DBLP]
ICCAD, 1996, pp:690-697 [Conf]
Sichao Wei, Pranab K. Nag, Ronald D. Blanton, Anne E. Gattiker, Wojciech Maly
To DFT or Not to DFT? [Citation Graph (0, 0)][DBLP]
ITC, 1997, pp:557-566 [Conf]
Peng Li, Pranab K. Nag, Wojciech Maly
Cost based tradeoff analysis of standard cell designs. [Citation Graph (0, 0)][DBLP]
SLIP, 2000, pp:129-135 [Conf]
Jitendra Khare, Sujoy Mitra, Pranab K. Nag, U. Maly, Rob A. Rutenbar
Testability-oriented channel routing. [Citation Graph (0, 0)][DBLP]
VLSI Design, 1995, pp:208-213 [Conf]
Pranab K. Nag, Anne E. Gattiker, Sichao Wei, Ronald D. Blanton, Wojciech Maly
Modeling the Economics of Testing: A DFT Perspective. [Citation Graph (0, 0)][DBLP]
IEEE Design & Test of Computers, 2002, v:19, n:1, pp:29-41 [Journal]

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