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Witold A. Pleskacz: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hans T. Heineken, Jitendra Khare, Wojciech Maly, Pranab K. Nag, Charles H. Ouyang, Witold A. Pleskacz
    CAD at the Design-Manufacturing Interface. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:321-326 [Conf]
  2. Zbigniew Piatek, Jerzy F. Kolodziejski, Witold A. Pleskacz
    ESD Failures of Integrated Circuits and Their Diagnostics Using Transmission Line Pulsing. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:423-428 [Conf]
  3. Artur L. Sobczyk, Arkadiusz W. Luczyk, Witold A. Pleskacz
    Power Dissipation in Basic Global Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:231-234 [Conf]
  4. Maksim Jenihhin, Jaan Raik, Raimund Ubar, Witold A. Pleskacz, Michal Rakowski
    Layout to Logic Defect Analysis for Hierarchical Test Generation. [Citation Graph (0, 0)][DBLP]
    DDECS, 2007, pp:35-40 [Conf]
  5. Witold A. Pleskacz
    Yield Estimation of VLSI Circuits with Downscaled Layouts. [Citation Graph (0, 0)][DBLP]
    DFT, 1999, pp:55-60 [Conf]
  6. Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz
    CMOS Standard Cells Characterization for IDDQ Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2002, pp:390-398 [Conf]
  7. Witold A. Pleskacz, Dominik Kasprowicz, Tomasz Oleszczak, Wieslaw Kuzmicz
    CMOS Standard Cells Characterization for Defect Based Testing. [Citation Graph (0, 0)][DBLP]
    DFT, 2001, pp:384-0 [Conf]
  8. Witold A. Pleskacz, Wojciech Maly
    Improved Yield Model for Submicron Domain. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:2-10 [Conf]
  9. Witold A. Pleskacz, Wojciech Maly, Hans T. Heineken
    Detection of Yield Trends. [Citation Graph (0, 0)][DBLP]
    DFT, 1997, pp:62-68 [Conf]
  10. Joachim Sudbrock, Jaan Raik, Raimund Ubar, Wieslaw Kuzmicz, Witold A. Pleskacz
    Defect-Oriented Test- and Layout-Generation for Standard-Cell ASIC Designs. [Citation Graph (0, 0)][DBLP]
    DSD, 2005, pp:79-82 [Conf]
  11. Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Defect-Oriented Fault Simulation and Test Generation in Digital Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:365-371 [Conf]
  12. Witold A. Pleskacz, Charles H. Ouyang, Wojciech Maly
    A DRC-based algorithm for extraction of critical areas for opens in large VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:2, pp:151-162 [Journal]
  13. Mykola Blyzniuk, Irena Kazymyra, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Probabilistic analysis of CMOS physical defects in VLSI circuits for test coverage improvement. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2001, v:41, n:12, pp:2023-2040 [Journal]
  14. T. Cibáková, M. Fischerová, Elena Gramatová, Wieslaw Kuzmicz, Witold A. Pleskacz, Jaan Raik, Raimund Ubar
    Hierarchical test generation for combinational circuits with real defects coverage. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2002, v:42, n:7, pp:1141-1149 [Journal]
  15. Dominik Kasprowicz, Witold A. Pleskacz
    Improvement of integrated circuit testing reliability by using the defect based approach. [Citation Graph (0, 0)][DBLP]
    Microelectronics Reliability, 2003, v:43, n:6, pp:945-953 [Journal]

  16. Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. [Citation Graph (, )][DBLP]


  17. Enhanced LEON3 core for superscalar processing. [Citation Graph (, )][DBLP]


  18. MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. [Citation Graph (, )][DBLP]


  19. Controllable Local Clock Signal Generator for Deep Submicron GALS Architectures. [Citation Graph (, )][DBLP]


  20. Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Technology. [Citation Graph (, )][DBLP]


  21. A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations. [Citation Graph (, )][DBLP]


  22. Various MDCT implementations in 0.35µm CMOS. [Citation Graph (, )][DBLP]


  23. Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. [Citation Graph (, )][DBLP]


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