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Keerthi Heragu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal
    An Efficient Path Delay Fault Coverage Estimator. [Citation Graph (0, 0)][DBLP]
    DAC, 1994, pp:516-521 [Conf]
  2. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    SIGMA: a simulator for segment delay faults. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1996, pp:502-508 [Conf]
  3. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Fast identification of untestable delay faults using implications. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:642-647 [Conf]
  4. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Statistical methods for delay fault coverage analysis. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1995, pp:166-170 [Conf]
  5. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Improving accuracy in path delay fault coverage estimation. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1996, pp:422-425 [Conf]
  6. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    A Test Generator for Segment Delay Faults. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:484-491 [Conf]
  7. Keerthi Heragu
    Where We Might Stumble with Embedded-System Test. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:470- [Conf]
  8. Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal
    Segment delay faults: a new fault model. [Citation Graph (0, 0)][DBLP]
    VTS, 1996, pp:32-41 [Conf]
  9. Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton
    Testing of Dynamic Logic Circuits Based on Charge Sharing. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:396-403 [Conf]
  10. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell
    Fault coverage estimation by test vector sampling. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:5, pp:590-596 [Journal]
  11. Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel
    Improving a nonenumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:7, pp:759-762 [Journal]
  12. Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton
    Test vector generation for charge sharing failures in dynamic logic. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:12, pp:1502-1508 [Journal]

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