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Gopalakrishnan Vijayan :
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Jan-Ming Ho , Gopalakrishnan Vijayan , C. K. Wong A New Approach to the Rectilinear Steiner Tree Problem. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:161-166 [Conf ] G. Vijayan Min-cost Partitioning on a Tree Structure and Applications. [Citation Graph (0, 0)][DBLP ] DAC, 1989, pp:771-774 [Conf ] Sergey Gavrilov , Alexey Glebov , Satyamurthy Pullela , S. C. Moore , Abhijit Dharchoudhury , Rajendran Panda , G. Vijayan , David Blaauw Library-less synthesis for static CMOS combinational logic circuits. [Citation Graph (0, 0)][DBLP ] ICCAD, 1997, pp:658-662 [Conf ] Gopalakrishnan Vijayan , Ren-Song Tsay Floorplanning by Topological Constraint Reduction. [Citation Graph (0, 0)][DBLP ] ICCAD, 1990, pp:106-109 [Conf ] Pradip Bose , David LaPotin , Gopalakrishnan Vijayan , SungHo Kim Workload-Driven Floorplanning for MIPS Optimization. [Citation Graph (0, 0)][DBLP ] ICCD, 1992, pp:387-391 [Conf ] Vinod Narayananan , David LaPotin , Rajesh K. Gupta , Gopalakrishnan Vijayan PEPPER - a timing driven early floorplanner. [Citation Graph (0, 0)][DBLP ] ICCD, 1995, pp:230-235 [Conf ] Vijay S. Iyengar , Gopalakrishnan Vijayan Test Application Timing: The Unexplored Issue in AC Test. [Citation Graph (0, 0)][DBLP ] ITC, 1991, pp:840-847 [Conf ] Gopalakrishnan Vijayan , Avi Wigderson Rectilinear Graphs and their Embeddings. [Citation Graph (0, 0)][DBLP ] SIAM J. Comput., 1985, v:14, n:2, pp:355-372 [Journal ] Gopalakrishnan Vijayan Generalization of Min-Cut Partitioning to Tree Structures and Its Applications. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 1991, v:40, n:3, pp:307-314 [Journal ] Jan-Ming Ho , Majid Sarrafzadeh , Gopalakrishnan Vijayan , Chak-Kuen Wong Pad minimization for planar routing of multiple power nets. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:4, pp:419-426 [Journal ] Jan-Ming Ho , Majid Sarrafzadeh , Gopalakrishnan Vijayan , Chak-Kuen Wong Layer assignment for multichip modules. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1272-1277 [Journal ] Jan-Ming Ho , Gopalakrishnan Vijayan , Chak-Kuen Wong New algorithms for the rectilinear Steiner tree problem. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:185-193 [Journal ] Vijay S. Iyengar , Gopalakrishnan Vijayan Optimized test application timing for AC test. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:11, pp:1439-1449 [Journal ] Gopalakrishnan Vijayan Partitioning logic on graph structures to minimize routing cost. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:12, pp:1326-1334 [Journal ] Gopalakrishnan Vijayan , H. H. Chen , Chak-Kuen Wong On VHV-routing in channels with irregular boundaries. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:2, pp:146-152 [Journal ] Gopalakrishnan Vijayan , Ren-Song Tsay A new method for floor planning using topological constraint reduction. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:12, pp:1494-1501 [Journal ] Richard J. Lipton , Jacobo Valdes , Gopalakrishnan Vijayan , Stephen C. North , Robert Sedgewick VLSI Layout as Programming. [Citation Graph (0, 0)][DBLP ] ACM Trans. Program. Lang. Syst., 1983, v:5, n:3, pp:405-421 [Journal ] Fast power loss calculation for digital static CMOS circuits. [Citation Graph (, )][DBLP ] On an edge ranking problem of trees and graphs. [Citation Graph (, )][DBLP ] Search in 0.002secs, Finished in 0.003secs