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Chi-Yi Hwang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
    LiB: A Cell Layout Generator. [Citation Graph (0, 0)][DBLP]
    DAC, 1990, pp:474-479 [Conf]
  2. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:481-486 [Conf]
  3. Min-Siang Lin, Hourng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
    Channel Density Reduction by Routing Over The Cells. [Citation Graph (0, 0)][DBLP]
    DAC, 1991, pp:120-125 [Conf]
  4. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Ping Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Scheme for System-On-Chip Designs. [Citation Graph (0, 0)][DBLP]
    DATE, 2002, pp:486-490 [Conf]
  5. Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pin Su, Cheng-Wen Wu, Chuang Cheng, Shao-I Chen, Chi-Yi Hwang, Hsiao-Ping Lin
    A Hierarchical Test Methodology for Systems on Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2002, v:22, n:5, pp:69-81 [Journal]
  6. Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu
    LiB: a CMOS cell compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:994-1005 [Journal]
  7. Chi-Yi Hwang, Yung-Chin Hsieh, Youn-Long Lin, Yu-Chin Hsu
    A fast transistor-chaining algorithm for CMOS cell layout. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:7, pp:781-786 [Journal]
  8. Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu
    An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:3, pp:410-424 [Journal]
  9. Min-Siang Lin, Houng-Wern Perng, Chi-Yi Hwang, Youn-Long Lin
    Channel density reduction by routing over the cells. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1991, v:10, n:8, pp:1067-1071 [Journal]

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