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Fur-Shing Tsai: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yu-Chin Hsu, Bassam Tabbara, Yirng-An Chen, Fur-Shing Tsai
    Advanced techniques for RTL debugging. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:362-367 [Conf]
  2. Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai Chang
    Visibility enhancement for silicon debug. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:13-18 [Conf]
  3. Fur-Shing Tsai, Yu-Chin Hsu
    Data Path Construction and Refinement. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:308-311 [Conf]
  4. Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Post-routing timing optimization with routing characterization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:30-35 [Conf]
  5. Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Timing optimization on routed designs with incremental placementand routing characterization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:2, pp:188-196 [Journal]
  6. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    SILK: a simulated evolution router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:10, pp:1108-1114 [Journal]
  7. Youn-Long Lin, Yu-Chin Hsu, Fur-Shing Tsai
    Hybrid routing. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1990, v:9, n:2, pp:151-157 [Journal]
  8. Fur-Shing Tsai, Yu-Chin Hsu
    STAR: An automatic data path allocator. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1992, v:11, n:9, pp:1053-1064 [Journal]
  9. Shi-Zheng Eric Lin, Chieh Changfan, Yu-Chin Hsu, Fur-Shing Tsai
    Optimal time borrowing analysis and timing budgeting optimization for latch-based designs. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:1, pp:217-230 [Journal]

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