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Shrirang K. Karandikar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Shiyan Hu, Charles J. Alpert, Jiang Hu, Shrirang K. Karandikar, Zhuo Li, Weiping Shi, Cliff C. N. Sze
    Fast algorithms for slew constrained minimum cost buffering. [Citation Graph (0, 0)][DBLP]
    DAC, 2006, pp:308-313 [Conf]
  2. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect. [Citation Graph (0, 0)][DBLP]
    DAC, 2001, pp:377-382 [Conf]
  3. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Fast Comparisons of Circuit Implementations. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:910-915 [Conf]
  4. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Logical effort based technology mapping. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:419-422 [Conf]
  5. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Fast comparisons of circuit implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:12, pp:1329-1339 [Journal]
  6. Charles J. Alpert, Shrirang K. Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T. Quay, Haoxing Ren, Cliff C. N. Sze, Paul G. Villarrubia, Mehmet Can Yildiz
    The nuts and bolts of physical synthesis. [Citation Graph (0, 0)][DBLP]
    SLIP, 2007, pp:89-94 [Conf]
  7. Shrirang K. Karandikar, Sachin S. Sapatnekar
    Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1094-1105 [Journal]

  8. Fast Electrical Correction Using Resizing and Buffering. [Citation Graph (, )][DBLP]


  9. Fast estimation of area-delay trade-offs in circuit sizing. [Citation Graph (, )][DBLP]


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