The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Chung-Yang Huang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Chung-Yang Huang, Kwang-Ting Cheng
    Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. [Citation Graph (0, 0)][DBLP]
    DAC, 2000, pp:118-123 [Conf]
  2. Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng
    LIBRA - a library-independent framework for post-layout performance optimization. [Citation Graph (0, 0)][DBLP]
    ISPD, 1998, pp:135-140 [Conf]
  3. Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng
    Static property checking using ATPG vs. BDD techniques. [Citation Graph (0, 0)][DBLP]
    ITC, 2000, pp:309-316 [Conf]
  4. Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer
    AQUILA: An Equivalence Checking System for Large Sequential Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:5, pp:443-464 [Journal]
  5. Chung-Yang Huang, Kwang-Ting Cheng
    Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2001, v:20, n:3, pp:381-391 [Journal]
  6. Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang
    QuteSAT: a robust circuit-based SAT solver for complex circuit structure. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1313-1318 [Conf]

  7. SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. [Citation Graph (, )][DBLP]


  8. A false-path aware formal static timing analyzer considering simultaneous input transitions. [Citation Graph (, )][DBLP]


  9. Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. [Citation Graph (, )][DBLP]


  10. Scalable exploration of functional dependency by interpolation and incremental SAT solving. [Citation Graph (, )][DBLP]


  11. Interpolant generation without constructing resolution graph. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.004secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002