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Chung-Wen Albert Tsao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Dennis J.-H. Huang, Andrew B. Kahng, Chung-Wen Albert Tsao
    On the Bounded-Skew Clock and Steiner Routing Problems. [Citation Graph (0, 0)][DBLP]
    DAC, 1995, pp:508-513 [Conf]
  2. Andrew B. Kahng, Chung-Wen Albert Tsao
    More Practical Bounded-Skew Clock Routing. [Citation Graph (0, 0)][DBLP]
    DAC, 1997, pp:594-599 [Conf]
  3. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing under Elmore delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:66-71 [Conf]
  4. Andrew B. Kahng, Chung-Wen Albert Tsao
    Low-cost single-layer clock trees with exact zero Elmore delay skew. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:213-218 [Conf]
  5. Chung-Wen Albert Tsao, Cheng-Kok Koh
    UST/DME: A Clock Tree Router for General Skew Constraints. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2000, pp:400-405 [Conf]
  6. Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Power Supply Noise Suppression via Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:355-360 [Conf]
  7. Wai-Ching Douglas Lam, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Clock Scheduling for Power Supply Noise Suppression using Genetic Algorithm with Selective Gene Therapy. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:327-332 [Conf]
  8. Andrew B. Kahng, Chung-Wen Albert Tsao
    Planar-DME: a single-layer zero-skew clock tree router. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:1, pp:8-19 [Journal]
  9. Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao
    Bounded-skew clock and Steiner routing. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 1998, v:3, n:3, pp:341-388 [Journal]
  10. Chung-Wen Albert Tsao, Cheng-Kok Koh
    UST/DME: a clock tree router for general skew constraints. [Citation Graph (0, 0)][DBLP]
    ACM Trans. Design Autom. Electr. Syst., 2002, v:7, n:3, pp:359-379 [Journal]

  11. Planar-DME: improved planar zero-skew clock routing with minimum pathlength delay. [Citation Graph (, )][DBLP]


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