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Herman Schmit: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Christopher Inacio, Herman Schmit, David Nagle, Andrew Ryan, Donald E. Thomas, Yingfai Tong, Ben Klass
    Vertical Benchmarks for CAD. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:408-413 [Conf]
  2. Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, V. Rovner, K. Y. Tong
    Exploring regular fabrics to optimize the performance-cost trade-off. [Citation Graph (0, 0)][DBLP]
    DAC, 2003, pp:782-787 [Conf]
  3. R. Reed Taylor, Herman Schmit
    Enabling energy efficiency in via-patterned gate array devices. [Citation Graph (0, 0)][DBLP]
    DAC, 2004, pp:874-878 [Conf]
  4. David Whelihan, Herman Schmit
    Memory optimization in single chip network switch fabrics. [Citation Graph (0, 0)][DBLP]
    DAC, 2002, pp:530-535 [Conf]
  5. Vikas Chandra, Anthony Xu, Herman Schmit, Lawrence T. Pileggi
    An Interconnect Channel Design Methodology for High Performance Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 2004, pp:1138-1143 [Conf]
  6. Aneesh Koorapaty, Vikas Chandra, K. Y. Tong, Chetan Patel, Lawrence T. Pileggi, Herman Schmit
    Heterogeneous Programmable Logic Block Architectures. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:11118-11119 [Conf]
  7. Hiroto Kagotani, Herman Schmit
    Asynchronous PipeRench: Architecture and Performance Estimations. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:121-0 [Conf]
  8. Ronald Laufer, R. Reed Taylor, Herman Schmit
    PCI-PipeRench and the SWORDAPI: A System for Stream-Based Reconfigurable Computing. [Citation Graph (0, 0)][DBLP]
    FCCM, 1999, pp:200-208 [Conf]
  9. Benjamin A. Levine, Herman Schmit
    Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable. [Citation Graph (0, 0)][DBLP]
    FCCM, 2003, pp:101-110 [Conf]
  10. Benjamin A. Levine, R. Reed Taylor, Herman Schmit
    Implementation of Near Shannon Limit Error-Correcting Codes Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2000, pp:217-226 [Conf]
  11. Matthew Moe, Herman Schmit, Seth Copen Goldstein
    Characterization and Parameterization of a Pipeline Reconfigurable FPGA. [Citation Graph (0, 0)][DBLP]
    FCCM, 1998, pp:294-0 [Conf]
  12. Herman Schmit
    Incremental reconfiguration for pipelined applications. [Citation Graph (0, 0)][DBLP]
    FCCM, 1997, pp:47-55 [Conf]
  13. Herman Schmit, Benjamin A. Levine, Benjamin Ylvisaker
    Queue Machines: Hardware Compilation in Hardware. [Citation Graph (0, 0)][DBLP]
    FCCM, 2002, pp:152-0 [Conf]
  14. Herman Schmit, Donald E. Thomas
    Hidden Markov modeling and fuzzy controllers in FPGAs. [Citation Graph (0, 0)][DBLP]
    FCCM, 1995, pp:214-221 [Conf]
  15. Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas
    Managing Pipeline-Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1998, pp:55-64 [Conf]
  16. Herman Schmit
    Is Reconfigurable Computing Commercially Viable (panel)? [Citation Graph (0, 0)][DBLP]
    FPGA, 1997, pp:101- [Conf]
  17. Herman Schmit
    Extra-Dimensional Island-Style FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 1999, pp:247- [Conf]
  18. Herman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate
    The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers. [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:101- [Conf]
  19. Herman Schmit, Vikas Chandra
    FPGA switch block layout and evaluation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2002, pp:11-18 [Conf]
  20. Herman Schmit, David Whelihan, Peter Kamarchik, Frank Gennari
    Scalable interconnect and power distribution for island-style FPGAs (poster abstract). [Citation Graph (0, 0)][DBLP]
    FPGA, 2000, pp:221- [Conf]
  21. Silviu M. S. A. Chiricescu, Michael A. Schuette, Robin Glinton, Herman Schmit
    Morphable Multipliers. [Citation Graph (0, 0)][DBLP]
    FPL, 2002, pp:647-656 [Conf]
  22. Aneesh Koorapaty, Lawrence T. Pileggi, Herman Schmit
    Heterogeneous Logic Block Architectures for Via-Patterned Programmable Fabrics. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:426-436 [Conf]
  23. Herman Schmit
    Extra-dimensional Island-Style FPGAs. [Citation Graph (0, 0)][DBLP]
    FPL, 2003, pp:406-415 [Conf]
  24. Vikas Chandra, Herman Schmit, Anthony Xu, Lawrence T. Pileggi
    A power aware system level interconnect design methodology for latency-insensitive systems. [Citation Graph (0, 0)][DBLP]
    ICCAD, 2004, pp:275-282 [Conf]
  25. Herman Schmit, Donald E. Thomas
    Address generation for memories containing multiple arrays. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1995, pp:510-514 [Conf]
  26. Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer
    PipeRench: A Coprocessor for Streaming multimedia Acceleration. [Citation Graph (0, 0)][DBLP]
    ISCA, 1999, pp:28-39 [Conf]
  27. Bharath Ramasubramanian, Herman Schmit, L. Richard Carley
    Mixed-swing quadrail for low power dual-rail domino logic. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1999, pp:82-84 [Conf]
  28. R. Reed Taylor, Herman Schmit
    Creating a power-aware structured ASIC. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:74-77 [Conf]
  29. Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi
    An architectural exploration of via patterned gate arrays. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:184-189 [Conf]
  30. Matthew Moe, Herman Schmit
    Floorplanning of pipelined array modules using sequence pairs. [Citation Graph (0, 0)][DBLP]
    ISPD, 2003, pp:143-150 [Conf]
  31. Herman Schmit, Donald E. Thomas
    Array mapping in behavioral synthesis. [Citation Graph (0, 0)][DBLP]
    ISSS, 1995, pp:90-95 [Conf]
  32. Vikas Chandra, Herman Schmit
    Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:35-40 [Conf]
  33. Theo Theocharides, Greg M. Link, E. J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit
    Evaluating Alternative Implementations for LDPC Decoder Check Node Function. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2004, pp:77-82 [Conf]
  34. Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton
    Synthesis of Morphable Multipliers. [Citation Graph (0, 0)][DBLP]
    IWLS, 2002, pp:109-113 [Conf]
  35. Yuan C. Chou, Pazhani Pillai, Herman Schmit, John Paul Shen
    PipeRench implementation of the instruction path coprocessor. [Citation Graph (0, 0)][DBLP]
    MICRO, 2000, pp:147-158 [Conf]
  36. Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis
    SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. [Citation Graph (0, 0)][DBLP]
    MSE, 2001, pp:42-43 [Conf]
  37. Thomas Kroll, Herman Schmit, Dave Landis
    CAD Tool Support For A Multi-University Soc Certificate Program: The Digital Sandbox. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:47-48 [Conf]
  38. Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis
    The Sandbox Design Experience Course. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:39-40 [Conf]
  39. Vikas Chandra, Anthony Xu, Herman Schmit
    A low power approach to system level pipelined interconnect design. [Citation Graph (0, 0)][DBLP]
    SLIP, 2004, pp:45-52 [Conf]
  40. Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matthew Moe, R. Reed Taylor
    PipeRench: A Reconfigurable Architecture and Compiler. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2000, v:33, n:4, pp:70-77 [Journal]
  41. Donald E. Thomas, Jay K. Adams, Herman Schmit
    A Model and Methodology for Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1993, v:10, n:3, pp:6-15 [Journal]
  42. Herman Schmit, Donald E. Thomas
    Address generation for memories containing multiple arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:5, pp:377-385 [Journal]
  43. Herman Schmit, Vikas Chandra
    Layout techniques for FPGA switch blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:1, pp:96-105 [Journal]
  44. Herman Schmit, Donald E. Thomas
    Synthesis of application-specific memory designs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:1, pp:101-111 [Journal]

  45. Placement challenges for structured ASICs. [Citation Graph (, )][DBLP]


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