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Eby G. Friedman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yehea I. Ismail, Eby G. Friedman
    Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:721-724 [Conf]
  2. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Figures of Merit to Characterize the Importance of On-Chip Inductance. [Citation Graph (0, 0)][DBLP]
    DAC, 1998, pp:560-565 [Conf]
  3. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Equivalent Elmore Delay for RLC Trees. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:715-720 [Conf]
  4. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Maximizing Performance by Retiming and Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    DAC, 1999, pp:231-236 [Conf]
  5. José Luis Neves, Eby G. Friedman
    Optimal Clock Skew Scheduling Tolerant to Process Variations. [Citation Graph (0, 0)][DBLP]
    DAC, 1996, pp:623-628 [Conf]
  6. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    DATE, 1999, pp:643-649 [Conf]
  7. Dimitrios Velenis, Marios C. Papaefthymiou, Eby G. Friedman
    Reduced Delay Uncertainty in High Performance Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    DATE, 2003, pp:10068-10075 [Conf]
  8. Boris D. Andreev, Eby G. Friedman, Edward L. Titlebaum
    Efficient implementation of a complex ±1 multiplier. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:83-88 [Conf]
  9. Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
    Orthogonal code generator for 3G wireless transceivers. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:229-232 [Conf]
  10. Magdy A. El-Moursy, Eby G. Friedman
    Optimum wire sizing of RLC interconnect with repeaters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:27-32 [Conf]
  11. Magdy A. El-Moursy, Eby G. Friedman
    Shielding effect of on-chip interconnect inductance. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:165-170 [Conf]
  12. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Dynamic and Short-Circuit Power of CMOS Gates Driving Lossless Transmission Lines. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:39-44 [Conf]
  13. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:56-59 [Conf]
  14. Volkan Kursun, Eby G. Friedman
    Low swing dual threshold voltage domino logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:47-52 [Conf]
  15. Andrey V. Mezhiba, Eby G. Friedman
    Properties of on-chip inductive current loops. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:12-17 [Conf]
  16. Vasilis F. Pavlidis, Eby G. Friedman
    Interconnect delay minimization through interlayer via placement in 3-D ICs. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:20-25 [Conf]
  17. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny
    On-chip power distribution grids with multiple supply voltages for high performance integrated circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:2-7 [Conf]
  18. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
    Maximum effective distance of on-chip decoupling capacitors in power distribution grids. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:173-179 [Conf]
  19. Jonathan Rosenfeld, Eby G. Friedman
    Sensitivity evaluation of global resonant H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:192-197 [Conf]
  20. Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
    Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:314-317 [Conf]
  21. Radu M. Secareanu, Eby G. Friedman
    Transparent repeaters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:63-66 [Conf]
  22. Kevin T. Tang, Eby G. Friedman
    Noise estimation due to signal activity for capacitively coupled CMOS logic gates. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:171-176 [Conf]
  23. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Repeater insertion in tree structured inductive interconnect. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:420-424 [Conf]
  24. Ivan S. Kourtev, Eby G. Friedman
    Clock skew scheduling for improved reliability via quadratic programming. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:239-243 [Conf]
  25. Tolga Soyata, Eby G. Friedman
    Retiming with non-zero clock skew, variable register, and interconnect delay. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1994, pp:234-241 [Conf]
  26. Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
    Low power flexible Rake receivers for WCDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:97-100 [Conf]
  27. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
    Electrical and optical on-chip interconnects in scaled microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2514-2517 [Conf]
  28. Guoqing Chen, Eby G. Friedman
    Low power repeaters driving RLC interconnects with delay and bandwidth constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:596-599 [Conf]
  29. Brian S. Cherkauer, Eby G. Friedman
    The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2110-2113 [Conf]
  30. Brian S. Cherkauer, Eby G. Friedman
    Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:111-114 [Conf]
  31. Magdy A. El-Moursy, Eby G. Friedman
    Inductive interconnect width optimization for low power. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:273-276 [Conf]
  32. Eby G. Friedman
    Clock Distribution Design in VLSI Circuits. An Overview. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1475-1478 [Conf]
  33. Eby G. Friedman, Sung-Mo Kang, Eric A. Vittoz, David J. Allstot, Erik P. Harris, Ran-Hong Yan
    Forum: From 100 Milliwatts/MIPS to 10 Microwatts/MIPS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:1-6 [Conf]
  34. Mücahit Kozak, Eby G. Friedman
    Design and simulation of Fractional-N PLL frequency synthesizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:780-783 [Conf]
  35. Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra
    Cascode buffer for monolithic voltage conversion operating at high input supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:464-467 [Conf]
  36. Andrey V. Mezhiba, Eby G. Friedman
    Electrical characteristics of multi-layer power distribution grids. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:473-476 [Conf]
  37. José Luis Neves, Eby G. Friedman
    Circuit Synthesis of Clock Distribution Networks Based on Non-Zero Clock Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:175-178 [Conf]
  38. José Luis Neves, Eby G. Friedman
    Minimizing Power Dissipation in Non-Zero Skew-Based Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1576-1579 [Conf]
  39. Mikhail Popovich, Eby G. Friedman
    Noise coupling in multi-voltage power distribution systems with decoupling capacitors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:620-623 [Conf]
  40. Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernandez, Eby G. Friedman
    Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:612-615 [Conf]
  41. Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
    Integration of Clock Skew and Register Delays into a Retiming Algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1483-1486 [Conf]
  42. Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
    Monotonicity Constraints on Path Delays for Efficient Retiming with Localized Clock Skew and Variable Register Delay. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1748-1751 [Conf]
  43. Junmou Zhang, Simon R. Cooper, Andrew R. LaPietra, Michael W. Mattern, Robert M. Guidash, Eby G. Friedman
    A low power thyristor-based CMOS programmable delay element. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:769-772 [Conf]
  44. Kevin T. Tang, Eby G. Friedman
    Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:463-466 [Conf]
  45. Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
    A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:422-425 [Conf]
  46. Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner
    A universal CMOS voltage interface circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:242-245 [Conf]
  47. Kevin T. Tang, Eby G. Friedman
    Peak noise prediction in loosely coupled interconnect [VLSI circuits]. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:541-544 [Conf]
  48. Radu M. Secareanu, Eby G. Friedman
    A high precision CMOS current mirror/divider. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:314-317 [Conf]
  49. Yehea I. Ismail, Eby G. Friedman
    Repeater insertion in RLC lines for minimum propagation delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:404-407 [Conf]
  50. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Signal waveform characterization in RLC trees. [Citation Graph (0, 0)][DBLP]
    ISCAS (6), 1999, pp:190-193 [Conf]
  51. Volkan Kursun, Eby G. Friedman
    Forward body biased keeper for enhanced noise immunity in domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:917-920 [Conf]
  52. Magdy A. El-Moursy, Eby G. Friedman
    Exponentially tapered H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:601-604 [Conf]
  53. Junmou Zhang, Eby G. Friedman
    Effect of shield insertion on reducing crosstalk noise between coupled interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:529-532 [Conf]
  54. Volkan Kursun, Eby G. Friedman
    Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:417-420 [Conf]
  55. Junmou Zhang, Eby G. Friedman
    Decoupling technique and crosstalk analysis for coupled RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:521-524 [Conf]
  56. Roy Mader, Eby G. Friedman, Ami Litman, Ivan S. Kourtev
    Large scale clock skew scheduling techniques for improved reliability of digital synchronous VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:357-360 [Conf]
  57. Andrey V. Mezhiba, Eby G. Friedman
    Inductance/area/resistance tradeoffs in high performance power distribution grids. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:101-104 [Conf]
  58. Weize Xu, Eby G. Friedman
    A substrate noise circuit for accurately testing mixed-signal ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2002, pp:145-148 [Conf]
  59. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Power dissipated by CMOS gates driving lossless transmission lines. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1998, pp:139-142 [Conf]
  60. Kevin T. Tang, Eby G. Friedman
    Interconnect coupling noise in CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISPD, 1999, pp:48-53 [Conf]
  61. Volkan Kursun, Eby G. Friedman
    Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:104-109 [Conf]
  62. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:279-0 [Conf]
  63. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:517-521 [Conf]
  64. Andrey V. Mezhiba, Eby G. Friedman
    Inductive Characteristics of Power Distribution Grids in High Speed Integrated Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2002, pp:316-321 [Conf]
  65. Emre Salman, Eby G. Friedman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar
    Pessimism Reduction In Static Timing Analysis Using Interdependent Setup and Hold Times. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:159-164 [Conf]
  66. Mikhail Popovich, Eby G. Friedman
    Noise Aware Decoupling Capacitors for Multi-Voltage Power Distribution Systems. [Citation Graph (0, 0)][DBLP]
    ISQED, 2005, pp:334-339 [Conf]
  67. Boris D. Andreev, Edward L. Titlebaum, Eby G. Friedman
    Transformations of Signed-Binary Number Representations for Efficient VLSI Arithmetic. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2003, pp:70-75 [Conf]
  68. Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
    Managing static leakage energy in microprocessor functional units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:321-332 [Conf]
  69. Dimitrios Velenis, Eby G. Friedman
    Buffer Sizing for Crosstalk Induced Delay Uncertainty. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2004, pp:750-759 [Conf]
  70. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi
    Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP]
    SLIP, 2005, pp:13-20 [Conf]
  71. Andrey V. Mezhiba, Eby G. Friedman
    Scaling trends of on-chip Power distribution noise. [Citation Graph (0, 0)][DBLP]
    SLIP, 2002, pp:47-53 [Conf]
  72. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
  73. Magdy A. El-Moursy, Eby G. Friedman
    Optimum wire sizing of RLC interconnect with repeaters . [Citation Graph (0, 0)][DBLP]
    Integration, 2004, v:38, n:2, pp:205-225 [Journal]
  74. Kevin T. Tang, Eby G. Friedman
    Delay and noise estimation of CMOS logic gates driving coupled resistive-capacitive interconnections. [Citation Graph (0, 0)][DBLP]
    Integration, 2000, v:29, n:2, pp:131-165 [Journal]
  75. Yehea I. Ismail, Eby G. Friedman
    On the Extraction of On-Chip Inductance. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2003, v:12, n:1, pp:31-40 [Journal]
  76. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Inductance Effects in RLC Trees. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:305-0 [Journal]
  77. Dimitrios Velenis, Kevin T. Tang, Ivan S. Kourtev, V. Adler, F. Baez, Eby G. Friedman
    Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2002, v:11, n:3, pp:231-246 [Journal]
  78. Guoqing Chen, Eby G. Friedman
    An RLC interconnect model based on fourier analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:2, pp:170-183 [Journal]
  79. Yehea I. Ismail, Eby G. Friedman
    DTT: direct truncation of the transfer function - an alternative tomoment matching for tree structured interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:131-144 [Journal]
  80. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Equivalent Elmore delay for RLC trees. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:1, pp:83-97 [Journal]
  81. Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
    Retiming and clock scheduling for digital circuit optimization. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:2, pp:184-203 [Journal]
  82. Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.
    Incorporating interconnect, register, and clock distribution delays into the retiming process. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1997, v:16, n:1, pp:105-120 [Journal]
  83. Magdy A. El-Moursy, Eby G. Friedman
    Power characteristics of inductive interconnect. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:12, pp:1295-1306 [Journal]
  84. Magdy A. El-Moursy, Eby G. Friedman
    Shielding effect of on-chip interconnect inductance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:3, pp:396-400 [Journal]
  85. Magdy A. El-Moursy, Eby G. Friedman
    Exponentially tapered H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:971-975 [Journal]
  86. Guoqing Chen, Eby G. Friedman
    Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:2, pp:161-172 [Journal]
  87. Mikhail Popovich, Eby G. Friedman
    Decoupling capacitors for multi-voltage power distribution systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:3, pp:217-228 [Journal]
  88. Volkan Kursun, Eby G. Friedman
    Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:485-496 [Journal]
  89. Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman
    Substrate coupling in digital circuits in mixed-signal smart-power systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:67-78 [Journal]
  90. Andrey V. Mezhiba, Eby G. Friedman
    Scaling trends of on-chip power distribution noise. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:4, pp:386-394 [Journal]
  91. Andrey V. Mezhiba, Eby G. Friedman
    Impedance characteristics of power distribution grids in nanoscale integrated circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:11, pp:1148-1155 [Journal]
  92. Junmou Zhang, Eby G. Friedman
    Crosstalk modeling for coupled RLC interconnects with application to shield insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:6, pp:641-646 [Journal]
  93. Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra
    Monolithic voltage conversion in low-voltage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:863-867 [Journal]
  94. Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
    Substrate Noise Reduction Based On Noise Aware Cell Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3227-3230 [Conf]
  95. Jonathan Rosenfeld, Eby G. Friedman
    Quasi-Resonant Interconnects: A Low Power Design Methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:641-644 [Conf]
  96. Magdy A. El-Moursy, Eby G. Friedman
    Optimum wire tapering for minimum power dissipation in RLC interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  97. Michael Sotman, Avinoam Kolodny, Mikhail Popovich, Eby G. Friedman
    On-die decoupling capacitance: frequency domain analysis of activity radius. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  98. Jonathan Rosenfeld, Eby G. Friedman
    Design methodology for global resonant H-tree clock distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  99. Guoqing Chen, Eby G. Friedman
    Effective capacitance of RLC loads for estimating short-circuit power. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  100. Vasilis F. Pavlidis, Eby G. Friedman
    Via placement for minimum interconnect delay in three-dimensional (3D) circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  101. Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson, David H. Albonesi, Philippe M. Fauchet, Eby G. Friedman
    Predictions of CMOS compatible on-chip optical interconnect. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:434-446 [Journal]
  102. Magdy A. El-Moursy, Eby G. Friedman
    Wire shaping of RLC interconnects. [Citation Graph (0, 0)][DBLP]
    Integration, 2007, v:40, n:4, pp:461-472 [Journal]
  103. Jonathan Rosenfeld, Eby G. Friedman
    Design Methodology for Global Resonant H-Tree Clock Distribution Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:2, pp:135-148 [Journal]
  104. Vasilis F. Pavlidis, Eby G. Friedman
    3-D Topologies for Networks-on-Chip. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1081-1090 [Journal]
  105. Brian S. Cherkauer, Eby G. Friedman
    Channel width tapering of serially connected MOSFET's with emphasis on power dissipation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1994, v:2, n:1, pp:100-114 [Journal]
  106. Brian S. Cherkauer, Eby G. Friedman
    A unified design methodology for CMOS tapered buffers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1995, v:3, n:1, pp:99-111 [Journal]
  107. José Luis Neves, Eby G. Friedman
    Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1996, v:4, n:2, pp:286-291 [Journal]
  108. Yehea I. Ismail, Eby G. Friedman, José Luis Neves
    Figures of merit to characterize the importance of on-chip inductance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1999, v:7, n:4, pp:442-449 [Journal]
  109. Yehea I. Ismail, Eby G. Friedman
    Effects of inductance on the propagation delay and repeater insertion in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2000, v:8, n:2, pp:195-206 [Journal]
  110. Yehea I. Ismail, Eby G. Friedman, J. L. Neves
    Exploiting the on-chip inductance in high-speed clock distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:6, pp:963-973 [Journal]
  111. Kevin T. Tang, Eby G. Friedman
    Simultaneous switching noise in on-chip CMOS power distribution networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:4, pp:487-493 [Journal]
  112. Andrey V. Mezhiba, Eby G. Friedman
    Inductive properties of high-performance power distribution grids. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:762-776 [Journal]
  113. Volkan Kursun, Eby G. Friedman
    Domino logic with variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1080-1093 [Journal]
  114. Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
    Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:514-522 [Journal]

  115. Simultaneous shield and repeater insertion. [Citation Graph (, )][DBLP]


  116. Power efficient tree-based crosslinks for skew reduction. [Citation Graph (, )][DBLP]


  117. Contact merging algorithm for efficient substrate noise analysis in large scale circuits. [Citation Graph (, )][DBLP]


  118. Design challenges in high performance three-dimensional circuits. [Citation Graph (, )][DBLP]


  119. Line width optimization for interdigitated power/ground networks. [Citation Graph (, )][DBLP]


  120. On-chip point-of-load voltage regulator for distributed power supplies. [Citation Graph (, )][DBLP]


  121. Timing-driven variation-aware nonuniform clock mesh synthesis. [Citation Graph (, )][DBLP]


  122. Methodology to achieve higher tolerance to delay variations in synchronous circuits. [Citation Graph (, )][DBLP]


  123. Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. [Citation Graph (, )][DBLP]


  124. An intra-chip free-space optical interconnect. [Citation Graph (, )][DBLP]


  125. A Fourier series-based RLC interconnect model for periodic signals. [Citation Graph (, )][DBLP]


  126. Equivalent rise time for resonance in power/ground noise estimation. [Citation Graph (, )][DBLP]


  127. Transient simulation of on-chip transmission lines via exact pole extraction. [Citation Graph (, )][DBLP]


  128. Input port reduction for efficient substrate extraction in large scale IC's. [Citation Graph (, )][DBLP]


  129. Electrical modeling and characterization of 3-D vias. [Citation Graph (, )][DBLP]


  130. On-chip DC-DC converters for three-dimensional ICs. [Citation Graph (, )][DBLP]


  131. Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. [Citation Graph (, )][DBLP]


  132. Timing optimization in logic with interconnect. [Citation Graph (, )][DBLP]


  133. Nanoscale on-chip decoupling capacitors. [Citation Graph (, )][DBLP]


  134. Pseudo-random clocking to enhance signal integrity. [Citation Graph (, )][DBLP]


  135. A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. [Citation Graph (, )][DBLP]


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